[Mesa-dev] [PATCH] i965/vec4: Don't coalesce registers in gen6 math ops if reswizzling needed

[Antía Puentes]

On mar, 2015-09-22 at 11:22 +0200, Antía Puentes wrote:
> I realized that if writemasking is also unsupported I should probably
> update the patch to avoid coalescing if the dst_writemask parameter is
> different from XYWZ. The condition in "vec4_instruction::can_reswizzle"
> would be something like:
> 
>   /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
>    * or writemasking are not allowed. */
>    if (devinfo->gen == 6 && is_math() &&
>        swizzle != BRW_SWIZZLE_XYZW &&
>        dst_writemask != WRITEMASK_XYWZ)
>       return false;

Ups, I meant: (swizzle != BRW_SWIZZLE_XYZW || dst_writemask !=
WRITEMASK_XYWZ)
Sorry for the noise.