[Mesa-dev] [PATCH 2/3] i965: make pull constant loads in gen6 start at MRFs 16/17
Iago Toral Quiroga
itoral at igalia.com
Tue Sep 22 05:00:58 PDT 2015
So they do not conflict with our (un)spills (MRF 21..23) or our
URB writes (MRF 1..15)
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 81fe7f5..e42cc94 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -50,6 +50,8 @@
#include "glsl/glsl_types.h"
#include "program/sampler.h"
+#define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
+
using namespace brw;
void
@@ -210,7 +212,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder &bld,
inst->regs_written = regs_written;
if (devinfo->gen < 7) {
- inst->base_mrf = 13;
+ inst->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->gen);
inst->header_size = 1;
if (devinfo->gen == 4)
inst->mlen = 3;
@@ -3008,7 +3010,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
* else does except for register spill/unspill, which generates and
* uses its MRF within a single IR instruction.
*/
- inst->base_mrf = 14;
+ inst->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->gen) + 1;
inst->mlen = 1;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 514ccd6..17516f9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -27,6 +27,7 @@
#include "program/sampler.h"
#define FIRST_SPILL_MRF(gen) (gen == 6 ? 21 : 13)
+#define FIRST_PULL_LOAD_MRF(gen) (gen == 6 ? 16 : 13)
namespace brw {
@@ -1386,7 +1387,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
dst,
surf_index,
offset_reg);
- pull->base_mrf = FIRST_SPILL_MRF(devinfo->gen) + 1;
+ pull->base_mrf = FIRST_PULL_LOAD_MRF(devinfo->gen) + 1;
pull->mlen = 1;
}
--
1.9.1
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