[Mesa-dev] [PATCH 08/23] i965/vs: Fix a subtlety in the nr_attributes == 0 workaround.

[Kenneth Graunke]

nr_attributes is used to compute first_non_payload_grf, which is the
first register we're allowed to use for ordinary register allocation.

The hardware requires us to read at least one pair of values, but we're
completely free to overwrite that garbage register with whatever we like.

Instead of altering nr_attributes, we should alter urb_read_length, which
only affects the amount we ask the VF to read.  This should save us a
register in trivial cases (which admittedly isn't very useful).

While we're at it, improve the explanation in the comments.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_vs.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 16d7c41..b0d5b3b 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -194,14 +194,15 @@ brw_codegen_vs_prog(struct brw_context *brw,
       nr_attributes++;
    }
 
-   /* The BSpec says we always have to read at least one thing from the VF,
-    * and it appears that the hardware wedges otherwise.
-    */
    if (nr_attributes == 0 && !brw->intelScreen->compiler->scalar_vs)
       nr_attributes = 1;
 
+   /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
+    * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode.  Empirically, in
+    * vec4 mode, the hardware appears to wedge unless we read something.
+    */
+   prog_data.base.urb_read_length = DIV_ROUND_UP(MAX2(nr_attributes, 1), 2);
    prog_data.nr_attributes = nr_attributes;
-   prog_data.base.urb_read_length = DIV_ROUND_UP(nr_attributes, 2);
 
    /* Since vertex shaders reuse the same VUE entry for inputs and outputs
     * (overwriting the original contents), we need to make sure the size is
-- 
2.5.3