[Mesa-dev] [PATCH 10/23] i965/vs: Simplify fs_visitor's ATTR file.

[Matt Turner]

On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke <kenneth at whitecape.org> wrote:
> Previously, ATTR was indexed by VERT_ATTRIB_* slots; at the end of
> compilation, assign_vs_urb_setup() translated those into GRF units,
> and converted ATTR to HW_REGs.
>
> This patch moves the transslation earlier, making ATTR work in terms of
> GRF units from the beginning.  assign_vs_urb_setup() simply has to add
> the number of payload registers and push constants to obtain the final
> hardware GRF number.  (We can't do this earlier as those values aren't
> known.)
>
> ATTR still supports reg_offset; however, it's simply added to reg.
> It's not clear whether this is valuable or not.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp         | 27 +++++--------------
>  src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |  2 +-
>  src/mesa/drivers/dri/i965/brw_nir.c          | 40 ++++++++++++++++++++++++++++
>  3 files changed, 48 insertions(+), 21 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index e23cb18..76ceb5e 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -1522,9 +1522,11 @@ void
>  fs_visitor::assign_vs_urb_setup()
>  {
>     brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
> -   int grf, slot, channel, attr;
>
>     assert(stage == MESA_SHADER_VERTEX);
> +   int count = _mesa_bitcount_64(vs_prog_data->inputs_read);
> +   if (vs_prog_data->uses_vertexid || vs_prog_data->uses_instanceid)
> +      count++;
>
>     /* Each attribute is 4 regs. */
>     this->first_non_payload_grf += 4 * vs_prog_data->nr_attributes;
> @@ -1535,25 +1537,10 @@ fs_visitor::assign_vs_urb_setup()
>     foreach_block_and_inst(block, fs_inst, inst, cfg) {
>        for (int i = 0; i < inst->sources; i++) {
>           if (inst->src[i].file == ATTR) {
> -
> -            if (inst->src[i].reg == VERT_ATTRIB_MAX) {
> -               slot = vs_prog_data->nr_attributes - 1;
> -            } else {
> -               /* Attributes come in in a contiguous block, ordered by their
> -                * gl_vert_attrib value.  That means we can compute the slot
> -                * number for an attribute by masking out the enabled
> -                * attributes before it and counting the bits.
> -                */
> -               attr = inst->src[i].reg + inst->src[i].reg_offset / 4;
> -               slot = _mesa_bitcount_64(vs_prog_data->inputs_read &
> -                                        BITFIELD64_MASK(attr));
> -            }
> -
> -            channel = inst->src[i].reg_offset & 3;
> -
> -            grf = payload.num_regs +
> -               prog_data->curb_read_length +
> -               slot * 4 + channel;
> +            int grf = payload.num_regs +
> +                      prog_data->curb_read_length +
> +                      inst->src[i].reg +
> +                      inst->src[i].reg_offset;
>
>              inst->src[i].file = HW_REG;
>              inst->src[i].fixed_hw_reg =
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 47d7ae4..cac9fff 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -53,7 +53,7 @@ fs_reg *
>  fs_visitor::emit_vs_system_value(int location)
>  {
>     fs_reg *reg = new(this->mem_ctx)
> -      fs_reg(ATTR, VERT_ATTRIB_MAX, BRW_REGISTER_TYPE_D);
> +      fs_reg(ATTR, 4*_mesa_bitcount_64(prog->InputsRead), BRW_REGISTER_TYPE_D);

Heh. I'd probably just line wrap the type to let us put spaces around
the *. Not important in any case.

>     brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
>
>     switch (location) {
> diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
> index 56bd3d3..a5e8e14 100644
> --- a/src/mesa/drivers/dri/i965/brw_nir.c
> +++ b/src/mesa/drivers/dri/i965/brw_nir.c
> @@ -27,6 +27,34 @@
>  #include "glsl/nir/glsl_to_nir.h"
>  #include "program/prog_to_nir.h"
>
> +static bool
> +remap_vs_attrs(nir_block *block, void *closure)
> +{
> +   GLbitfield64 inputs_read = *((GLbitfield64 *) closure);
> +
> +   nir_foreach_instr(block, instr) {
> +      if (instr->type != nir_instr_type_intrinsic)
> +         continue;
> +
> +      nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
> +
> +      /* We set EmitNoIndirect for VS inputs, so there are no indirects. */
> +      assert(intrin->intrinsic != nir_intrinsic_load_input_indirect);
> +
> +      if (intrin->intrinsic == nir_intrinsic_load_input) {
> +         /* Attributes come in a contiguous block, ordered by their
> +          * gl_vert_attrib value.  That means we can compute the slot
> +          * number for an attribute by masking out the enabled attributes
> +          * before it and counting the bits.
> +          */
> +         int attr = intrin->const_index[0];
> +         int slot = _mesa_bitcount_64(inputs_read & BITFIELD64_MASK(attr));
> +         intrin->const_index[0] = 4 * slot;
> +      }
> +   }
> +   return true;
> +}
> +
>  static void
>  brw_nir_lower_inputs(nir_shader *nir,
>                       const struct gl_program *prog,
> @@ -51,6 +79,18 @@ brw_nir_lower_inputs(nir_shader *nir,
>         * type_size_vec4 here.
>         */
>        nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
> +
> +      /* Finally, translate VERT_ATTRIB_* values into the actual registers.
> +       *
> +       * Note that we can use prog->InputsRead rather than key->inputs_read,
> +       * since the two identical aside from Gen4-5 edge flag differences.

s/two/two are/