[Mesa-dev] [PATCH 12/23] i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.

[Matt Turner]

On Wed, Sep 30, 2015 at 12:58 AM, Kenneth Graunke <kenneth at whitecape.org> wrote:
> diff --git a/src/mesa/drivers/dri/i965/brw_inst.h b/src/mesa/drivers/dri/i965/brw_inst.h
> index c5132ba..b551334 100644
> --- a/src/mesa/drivers/dri/i965/brw_inst.h
> +++ b/src/mesa/drivers/dri/i965/brw_inst.h
> @@ -386,6 +386,7 @@ FF(urb_per_slot_offset,
>     /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
>     /* 7:   */ MD(16), MD(16),
>     /* 8:   */ MD(17), MD(17))
> +FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
>  FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
>  FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
>  FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)

Not related to your patch per se, but the write-complete bit is
totally gone from BDW+? Not necessary anymore?

What's going on in vec4_vs_visitor::emit_urb_write_opcode() then? I
couldn't convince myself that we wouldn't ever set the write-complete
bit on Gen8+ in that function...