[Mesa-dev] [PATCH 2/5] winsys/amdgpu: add support for 64-bit buffer sizes
Nicolai Hähnle
nhaehnle at gmail.com
Mon Apr 11 16:36:33 UTC 2016
On 11.04.2016 05:38, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/gallium/auxiliary/util/u_math.h | 6 ++++++
> src/gallium/drivers/radeon/radeon_winsys.h | 4 ++--
> src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 29 +++++++++++++-------------
> src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 2 +-
> src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 4 ++--
> 5 files changed, 26 insertions(+), 19 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_math.h b/src/gallium/auxiliary/util/u_math.h
> index e92f83a..77dc865 100644
> --- a/src/gallium/auxiliary/util/u_math.h
> +++ b/src/gallium/auxiliary/util/u_math.h
> @@ -792,6 +792,12 @@ align(int value, int alignment)
> return (value + alignment - 1) & ~(alignment - 1);
> }
>
> +static inline uint64_t
> +align64(uint64_t value, int alignment)
alignment should probably be unsigned for consistency.
Nicolai
> +{
> + return (value + alignment - 1) & ~(alignment - 1);
> +}
> +
> /**
> * Works like align but on npot alignments.
> */
> diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
> index baecca7..743dbd1 100644
> --- a/src/gallium/drivers/radeon/radeon_winsys.h
> +++ b/src/gallium/drivers/radeon/radeon_winsys.h
> @@ -449,7 +449,7 @@ struct radeon_winsys {
> * \return The created buffer object.
> */
> struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
> - unsigned size,
> + uint64_t size,
> unsigned alignment,
> boolean use_reusable_pool,
> enum radeon_bo_domain domain,
> @@ -528,7 +528,7 @@ struct radeon_winsys {
> * \param Size Size in bytes for the new buffer.
> */
> struct pb_buffer *(*buffer_from_ptr)(struct radeon_winsys *ws,
> - void *pointer, unsigned size);
> + void *pointer, uint64_t size);
>
> /**
> * Whether the buffer was created from a user pointer.
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> index c79bed4..04ef17d 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> @@ -36,6 +36,7 @@
> #include <amdgpu_drm.h>
> #include <xf86drm.h>
> #include <stdio.h>
> +#include <inttypes.h>
>
> static inline struct amdgpu_winsys_bo *amdgpu_winsys_bo(struct pb_buffer *bo)
> {
> @@ -141,9 +142,9 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
> amdgpu_fence_reference(&bo->fence[i], NULL);
>
> if (bo->initial_domain & RADEON_DOMAIN_VRAM)
> - bo->ws->allocated_vram -= align(bo->base.size, bo->ws->gart_page_size);
> + bo->ws->allocated_vram -= align64(bo->base.size, bo->ws->gart_page_size);
> else if (bo->initial_domain & RADEON_DOMAIN_GTT)
> - bo->ws->allocated_gtt -= align(bo->base.size, bo->ws->gart_page_size);
> + bo->ws->allocated_gtt -= align64(bo->base.size, bo->ws->gart_page_size);
> FREE(bo);
> }
>
> @@ -265,7 +266,7 @@ static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo *bo)
> }
>
> static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
> - unsigned size,
> + uint64_t size,
> unsigned alignment,
> unsigned usage,
> enum radeon_bo_domain initial_domain,
> @@ -303,9 +304,9 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
> r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle);
> if (r) {
> fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
> - fprintf(stderr, "amdgpu: size : %d bytes\n", size);
> - fprintf(stderr, "amdgpu: alignment : %d bytes\n", alignment);
> - fprintf(stderr, "amdgpu: domains : %d\n", initial_domain);
> + fprintf(stderr, "amdgpu: size : %"PRIu64" bytes\n", size);
> + fprintf(stderr, "amdgpu: alignment : %u bytes\n", alignment);
> + fprintf(stderr, "amdgpu: domains : %u\n", initial_domain);
> goto error_bo_alloc;
> }
>
> @@ -331,9 +332,9 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
> bo->unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
>
> if (initial_domain & RADEON_DOMAIN_VRAM)
> - ws->allocated_vram += align(size, ws->gart_page_size);
> + ws->allocated_vram += align64(size, ws->gart_page_size);
> else if (initial_domain & RADEON_DOMAIN_GTT)
> - ws->allocated_gtt += align(size, ws->gart_page_size);
> + ws->allocated_gtt += align64(size, ws->gart_page_size);
>
> amdgpu_add_buffer_to_global_list(bo);
>
> @@ -458,7 +459,7 @@ static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf,
>
> static struct pb_buffer *
> amdgpu_bo_create(struct radeon_winsys *rws,
> - unsigned size,
> + uint64_t size,
> unsigned alignment,
> boolean use_reusable_pool,
> enum radeon_bo_domain domain,
> @@ -482,7 +483,7 @@ amdgpu_bo_create(struct radeon_winsys *rws,
> * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
> * like constant/uniform buffers, can benefit from better and more reuse.
> */
> - size = align(size, ws->gart_page_size);
> + size = align64(size, ws->gart_page_size);
>
> /* Only set one usage bit each for domains and flags, or the cache manager
> * might consider different sets of domains / flags compatible
> @@ -592,9 +593,9 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
> *offset = whandle->offset;
>
> if (bo->initial_domain & RADEON_DOMAIN_VRAM)
> - ws->allocated_vram += align(bo->base.size, ws->gart_page_size);
> + ws->allocated_vram += align64(bo->base.size, ws->gart_page_size);
> else if (bo->initial_domain & RADEON_DOMAIN_GTT)
> - ws->allocated_gtt += align(bo->base.size, ws->gart_page_size);
> + ws->allocated_gtt += align64(bo->base.size, ws->gart_page_size);
>
> amdgpu_add_buffer_to_global_list(bo);
>
> @@ -648,7 +649,7 @@ static boolean amdgpu_bo_get_handle(struct pb_buffer *buffer,
> }
>
> static struct pb_buffer *amdgpu_bo_from_ptr(struct radeon_winsys *rws,
> - void *pointer, unsigned size)
> + void *pointer, uint64_t size)
> {
> struct amdgpu_winsys *ws = amdgpu_winsys(rws);
> amdgpu_bo_handle buf_handle;
> @@ -684,7 +685,7 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct radeon_winsys *rws,
> bo->initial_domain = RADEON_DOMAIN_GTT;
> bo->unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
>
> - ws->allocated_gtt += align(bo->base.size, ws->gart_page_size);
> + ws->allocated_gtt += align64(bo->base.size, ws->gart_page_size);
>
> amdgpu_add_buffer_to_global_list(bo);
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> index 4c837a8..1164a30 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
> @@ -212,7 +212,7 @@ static int compute_level(struct amdgpu_winsys *ws,
> }
>
> surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
> - surf_level->offset = align(surf->bo_size, AddrSurfInfoOut->baseAlign);
> + surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
> surf_level->slice_size = AddrSurfInfoOut->sliceSize;
> surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
> surf_level->npix_x = u_minify(surf->npix_x, level);
> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
> index c92a66e..2810dca 100644
> --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
> @@ -718,7 +718,7 @@ static void radeon_bo_set_metadata(struct pb_buffer *_buf,
>
> static struct pb_buffer *
> radeon_winsys_bo_create(struct radeon_winsys *rws,
> - unsigned size,
> + uint64_t size,
> unsigned alignment,
> boolean use_reusable_pool,
> enum radeon_bo_domain domain,
> @@ -769,7 +769,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
> }
>
> static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
> - void *pointer, unsigned size)
> + void *pointer, uint64_t size)
> {
> struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
> struct drm_radeon_gem_userptr args;
>
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