[Mesa-dev] [PATCH v2 01/20] radeonsi: lower compute shader arguments
eocallaghan at alterapraxis.com
eocallaghan at alterapraxis.com
Thu Apr 14 03:15:10 UTC 2016
Patches - 2-4, 7-8, 12-14 & 17 - are all:
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
The series was:
Tested-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
On 2016-04-14 05:29, Bas Nieuwenhuizen wrote:
> Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
> Reviewed-by: Marek Olšák <marek.olsak at amd.com>
> Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
> ---
> src/gallium/drivers/radeonsi/si_shader.c | 41
> ++++++++++++++++++++++++++++++++
> src/gallium/drivers/radeonsi/si_shader.h | 7 ++++++
> 2 files changed, 48 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> index c58467d..1ccdcac 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -1282,6 +1282,36 @@ static void declare_system_value(
> value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
> break;
>
> + case TGSI_SEMANTIC_GRID_SIZE:
> + value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
> + break;
> +
> + case TGSI_SEMANTIC_BLOCK_SIZE:
> + {
> + LLVMValueRef values[3];
> + unsigned i;
> + unsigned *properties = ctx->shader->selector->info.properties;
> + unsigned sizes[3] = {
> + properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
> + properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
> + properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
> + };
> +
> + for (i = 0; i < 3; ++i)
> + values[i] = lp_build_const_int32(gallivm, sizes[i]);
> +
> + value = lp_build_gather_values(gallivm, values, 3);
> + break;
> + }
> +
> + case TGSI_SEMANTIC_BLOCK_ID:
> + value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
> + break;
> +
> + case TGSI_SEMANTIC_THREAD_ID:
> + value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
> + break;
> +
> default:
> assert(!"unknown system value");
> return;
> @@ -4823,6 +4853,14 @@ static void create_function(struct
> si_shader_context *ctx)
> }
> break;
>
> + case TGSI_PROCESSOR_COMPUTE:
> + params[SI_PARAM_GRID_SIZE] = v3i32;
> + params[SI_PARAM_BLOCK_ID] = v3i32;
> + last_sgpr = SI_PARAM_BLOCK_ID;
> +
> + params[SI_PARAM_THREAD_ID] = v3i32;
> + num_params = SI_PARAM_THREAD_ID + 1;
> + break;
> default:
> assert(0 && "unimplemented shader");
> return;
> @@ -5600,6 +5638,7 @@ void si_dump_shader_key(unsigned shader, union
> si_shader_key *key, FILE *f)
> break;
>
> case PIPE_SHADER_GEOMETRY:
> + case PIPE_SHADER_COMPUTE:
> break;
>
> case PIPE_SHADER_FRAGMENT:
> @@ -5784,6 +5823,8 @@ int si_compile_tgsi_shader(struct si_screen
> *sscreen,
> else
> bld_base->emit_epilogue = si_llvm_return_fs_outputs;
> break;
> + case TGSI_PROCESSOR_COMPUTE:
> + break;
> default:
> assert(!"Unsupported shader type");
> return -1;
> diff --git a/src/gallium/drivers/radeonsi/si_shader.h
> b/src/gallium/drivers/radeonsi/si_shader.h
> index 013c8a2..5043d43 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.h
> +++ b/src/gallium/drivers/radeonsi/si_shader.h
> @@ -91,6 +91,7 @@ struct radeon_shader_reloc;
> #define SI_SGPR_TCS_OUT_LAYOUT 11 /* TCS & TES only */
> #define SI_SGPR_TCS_IN_LAYOUT 12 /* TCS only */
> #define SI_SGPR_ALPHA_REF 10 /* PS only */
> +#define SI_SGPR_GRID_SIZE 10 /* CS only */
>
> #define SI_VS_NUM_USER_SGPR 15 /* API VS */
> #define SI_ES_NUM_USER_SGPR 14 /* API VS */
> @@ -100,6 +101,7 @@ struct radeon_shader_reloc;
> #define SI_GS_NUM_USER_SGPR 10
> #define SI_GSCOPY_NUM_USER_SGPR 4
> #define SI_PS_NUM_USER_SGPR 11
> +#define SI_CS_NUM_USER_SGPR 13
>
> /* LLVM function parameter indices */
> #define SI_PARAM_RW_BUFFERS 0
> @@ -173,6 +175,11 @@ struct radeon_shader_reloc;
> #define SI_PARAM_SAMPLE_COVERAGE 21
> #define SI_PARAM_POS_FIXED_PT 22
>
> +/* CS only parameters */
> +#define SI_PARAM_GRID_SIZE 5
> +#define SI_PARAM_BLOCK_ID 6
> +#define SI_PARAM_THREAD_ID 7
> +
> #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 9) /* +8 for
> COLOR[0..1] */
>
> struct si_shader;
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