[Mesa-dev] [PATCH 05/13] radeonsi: Create CE IB.

[Nicolai Hähnle]

On 13.04.2016 20:34, Bas Nieuwenhuizen wrote:
> Based on work by Marek Olšák.
>
> Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
> ---
>   src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
>   src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
>   src/gallium/drivers/radeonsi/si_hw_context.c  | 4 +++-
>   src/gallium/drivers/radeonsi/si_pipe.c        | 7 +++++++
>   src/gallium/drivers/radeonsi/si_pipe.h        | 2 ++
>   5 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
> index a7477ab..a8660f2 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -402,6 +402,7 @@ static const struct debug_named_value common_debug_options[] = {
>   	{ "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
>   	{ "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction Scheduler." },
>   	{ "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders compiled on demand" },
> +	{ "noce", DBG_NO_CE, "Disable the constant engine"},
>
>   	DEBUG_NAMED_VALUE_END /* must be last */
>   };
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
> index a6abe09..dbbd98f 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -95,6 +95,7 @@
>   #define DBG_NO_RB_PLUS		(1llu << 45)
>   #define DBG_SI_SCHED		(1llu << 46)
>   #define DBG_MONOLITHIC_SHADERS	(1llu << 47)
> +#define DBG_NO_CE		(1llu << 48)
>
>   #define R600_MAP_BUFFER_ALIGNMENT 64
>   #define R600_MAX_VIEWPORTS        16
> diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
> index b621b55..9c84623 100644
> --- a/src/gallium/drivers/radeonsi/si_hw_context.c
> +++ b/src/gallium/drivers/radeonsi/si_hw_context.c
> @@ -30,6 +30,7 @@
>   void si_need_cs_space(struct si_context *ctx)
>   {
>   	struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
> +	struct radeon_winsys_cs *ce_ib = ctx->ce_ib;
>   	struct radeon_winsys_cs *dma = ctx->b.dma.cs;
>
>   	/* Flush the DMA IB if it's not empty. */
> @@ -53,7 +54,8 @@ void si_need_cs_space(struct si_context *ctx)
>   	/* If the CS is sufficiently large, don't count the space needed
>   	 * and just flush if there is not enough space left.
>   	 */
> -	if (unlikely(cs->cdw > cs->max_dw - 2048))
> +	if (unlikely(cs->cdw > cs->max_dw - 2048 ||
> +                     (ce_ib && ce_ib->cdw > ce_ib->max_dw - 10 * 1024)))
>   		ctx->b.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
>   }

Looking at si_init_all_descriptors, I believe we have up to 4184 dws of 
descriptors. Leaving some head room and space for the CE commands 
itself, you could probably get away with 5 * 1024. Anyway, I don't feel 
too strongly about this.

Nicolai

>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 6a990ed..e49836d 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -142,6 +142,13 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
>
>   	sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
>   				       si_context_gfx_flush, sctx);
> +
> +	if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
> +		sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
> +		if (!sctx->ce_ib)
> +			goto fail;
> +	}
> +
>   	sctx->b.gfx.flush = si_context_gfx_flush;
>
>   	/* Border colors. */
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index 0398b1d..743c782 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -191,6 +191,8 @@ struct si_context {
>   	void				*custom_blend_dcc_decompress;
>   	void				*pstipple_sampler_state;
>   	struct si_screen		*screen;
> +	struct radeon_winsys_cs		*ce_ib;
> +
>   	struct pipe_fence_handle	*last_gfx_fence;
>   	struct si_shader_ctx_state	fixed_func_tcs_shader;
>   	LLVMTargetMachineRef		tm;
>