[Mesa-dev] [PATCH 2/2] radeonsi: use enums in si_shader.h
Marek Olšák
maraeo at gmail.com
Sat Apr 16 12:50:35 UTC 2016
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_shader.h | 212 +++++++++++++++++--------------
1 file changed, 119 insertions(+), 93 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 013c8a2..dab572c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -77,103 +77,129 @@ struct radeon_shader_reloc;
#define SI_MAX_VS_OUTPUTS 40
-#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
-#define SI_SGPR_CONST_BUFFERS 2
-#define SI_SGPR_SAMPLERS 4 /* images & sampler states interleaved */
-#define SI_SGPR_IMAGES 6
-#define SI_SGPR_SHADER_BUFFERS 8
-#define SI_SGPR_VERTEX_BUFFERS 10 /* VS only */
-#define SI_SGPR_BASE_VERTEX 12 /* VS only */
-#define SI_SGPR_START_INSTANCE 13 /* VS only */
-#define SI_SGPR_VS_STATE_BITS 14 /* VS(VS) only */
-#define SI_SGPR_LS_OUT_LAYOUT 14 /* VS(LS) only */
-#define SI_SGPR_TCS_OUT_OFFSETS 10 /* TCS & TES only */
-#define SI_SGPR_TCS_OUT_LAYOUT 11 /* TCS & TES only */
-#define SI_SGPR_TCS_IN_LAYOUT 12 /* TCS only */
-#define SI_SGPR_ALPHA_REF 10 /* PS only */
-
-#define SI_VS_NUM_USER_SGPR 15 /* API VS */
-#define SI_ES_NUM_USER_SGPR 14 /* API VS */
-#define SI_LS_NUM_USER_SGPR 15 /* API VS */
-#define SI_TCS_NUM_USER_SGPR 13
-#define SI_TES_NUM_USER_SGPR 12
-#define SI_GS_NUM_USER_SGPR 10
-#define SI_GSCOPY_NUM_USER_SGPR 4
-#define SI_PS_NUM_USER_SGPR 11
+/* SGPR user data indices */
+enum {
+ SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
+ SI_SGPR_RW_BUFFERS_HI,
+ SI_SGPR_CONST_BUFFERS,
+ SI_SGPR_CONST_BUFFERS_HI,
+ SI_SGPR_SAMPLERS, /* images & sampler states interleaved */
+ SI_SGPR_SAMPLERS_HI,
+ SI_SGPR_IMAGES,
+ SI_SGPR_IMAGES_HI,
+ SI_SGPR_SHADER_BUFFERS,
+ SI_SGPR_SHADER_BUFFERS_HI,
+ SI_NUM_RESOURCE_SGPRS,
+
+ /* all VS variants */
+ SI_SGPR_VERTEX_BUFFERS = SI_NUM_RESOURCE_SGPRS,
+ SI_SGPR_VERTEX_BUFFERS_HI,
+ SI_SGPR_BASE_VERTEX,
+ SI_SGPR_START_INSTANCE,
+ SI_ES_NUM_USER_SGPR,
+
+ /* hw VS only */
+ SI_SGPR_VS_STATE_BITS = SI_ES_NUM_USER_SGPR,
+ SI_VS_NUM_USER_SGPR,
+
+ /* hw LS only */
+ SI_SGPR_LS_OUT_LAYOUT = SI_ES_NUM_USER_SGPR,
+ SI_LS_NUM_USER_SGPR,
+
+ /* both TCS and TES */
+ SI_SGPR_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_SGPRS,
+ SI_SGPR_TCS_OUT_LAYOUT,
+ SI_TES_NUM_USER_SGPR,
+
+ /* TCS only */
+ SI_SGPR_TCS_IN_LAYOUT = SI_TES_NUM_USER_SGPR,
+ SI_TCS_NUM_USER_SGPR,
+
+ /* GS limits */
+ SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
+ SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_CONST_BUFFERS_HI + 1,
+
+ /* PS only */
+ SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS,
+ SI_PS_NUM_USER_SGPR,
+};
/* LLVM function parameter indices */
-#define SI_PARAM_RW_BUFFERS 0
-#define SI_PARAM_CONST_BUFFERS 1
-#define SI_PARAM_SAMPLERS 2
-#define SI_PARAM_IMAGES 3
-#define SI_PARAM_SHADER_BUFFERS 4
-
-/* VS only parameters */
-#define SI_PARAM_VERTEX_BUFFERS 5
-#define SI_PARAM_BASE_VERTEX 6
-#define SI_PARAM_START_INSTANCE 7
-/* [0] = clamp vertex color */
-#define SI_PARAM_VS_STATE_BITS 8
-/* the other VS parameters are assigned dynamically */
-
-/* Offsets where TCS outputs and TCS patch outputs live in LDS:
- * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
- * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
- */
-#define SI_PARAM_TCS_OUT_OFFSETS 5 /* for TCS & TES */
+enum {
+ SI_PARAM_RW_BUFFERS,
+ SI_PARAM_CONST_BUFFERS,
+ SI_PARAM_SAMPLERS,
+ SI_PARAM_IMAGES,
+ SI_PARAM_SHADER_BUFFERS,
+ SI_NUM_RESOURCE_PARAMS,
+
+ /* VS only parameters */
+ SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_BASE_VERTEX,
+ SI_PARAM_START_INSTANCE,
+ /* [0] = clamp vertex color */
+ SI_PARAM_VS_STATE_BITS,
+ /* the other VS parameters are assigned dynamically */
+
+ /* Offsets where TCS outputs and TCS patch outputs live in LDS:
+ * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
+ * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
+ */
+ SI_PARAM_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
-/* Layout of TCS outputs / TES inputs:
- * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
- * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
- * [26:31] = gl_PatchVerticesIn, max = 32
- */
-#define SI_PARAM_TCS_OUT_LAYOUT 6 /* for TCS & TES */
+ /* Layout of TCS outputs / TES inputs:
+ * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
+ * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
+ * [26:31] = gl_PatchVerticesIn, max = 32
+ */
+ SI_PARAM_TCS_OUT_LAYOUT, /* for TCS & TES */
-/* Layout of LS outputs / TCS inputs
- * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
- * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
- */
-#define SI_PARAM_TCS_IN_LAYOUT 7 /* TCS only */
-#define SI_PARAM_LS_OUT_LAYOUT 8 /* same value as TCS_IN_LAYOUT, LS only */
-
-/* TCS only parameters. */
-#define SI_PARAM_TESS_FACTOR_OFFSET 8
-#define SI_PARAM_PATCH_ID 9
-#define SI_PARAM_REL_IDS 10
-
-/* GS only parameters */
-#define SI_PARAM_GS2VS_OFFSET 5
-#define SI_PARAM_GS_WAVE_ID 6
-#define SI_PARAM_VTX0_OFFSET 7
-#define SI_PARAM_VTX1_OFFSET 8
-#define SI_PARAM_PRIMITIVE_ID 9
-#define SI_PARAM_VTX2_OFFSET 10
-#define SI_PARAM_VTX3_OFFSET 11
-#define SI_PARAM_VTX4_OFFSET 12
-#define SI_PARAM_VTX5_OFFSET 13
-#define SI_PARAM_GS_INSTANCE_ID 14
-
-/* PS only parameters */
-#define SI_PARAM_ALPHA_REF 5
-#define SI_PARAM_PRIM_MASK 6
-#define SI_PARAM_PERSP_SAMPLE 7
-#define SI_PARAM_PERSP_CENTER 8
-#define SI_PARAM_PERSP_CENTROID 9
-#define SI_PARAM_PERSP_PULL_MODEL 10
-#define SI_PARAM_LINEAR_SAMPLE 11
-#define SI_PARAM_LINEAR_CENTER 12
-#define SI_PARAM_LINEAR_CENTROID 13
-#define SI_PARAM_LINE_STIPPLE_TEX 14
-#define SI_PARAM_POS_X_FLOAT 15
-#define SI_PARAM_POS_Y_FLOAT 16
-#define SI_PARAM_POS_Z_FLOAT 17
-#define SI_PARAM_POS_W_FLOAT 18
-#define SI_PARAM_FRONT_FACE 19
-#define SI_PARAM_ANCILLARY 20
-#define SI_PARAM_SAMPLE_COVERAGE 21
-#define SI_PARAM_POS_FIXED_PT 22
-
-#define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 9) /* +8 for COLOR[0..1] */
+ /* Layout of LS outputs / TCS inputs
+ * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
+ * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+ */
+ SI_PARAM_TCS_IN_LAYOUT, /* TCS only */
+ SI_PARAM_LS_OUT_LAYOUT, /* same value as TCS_IN_LAYOUT, LS only */
+
+ /* TCS only parameters. */
+ SI_PARAM_TESS_FACTOR_OFFSET = SI_PARAM_TCS_IN_LAYOUT + 1,
+ SI_PARAM_PATCH_ID,
+ SI_PARAM_REL_IDS,
+
+ /* GS only parameters */
+ SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_GS_WAVE_ID,
+ SI_PARAM_VTX0_OFFSET,
+ SI_PARAM_VTX1_OFFSET,
+ SI_PARAM_PRIMITIVE_ID,
+ SI_PARAM_VTX2_OFFSET,
+ SI_PARAM_VTX3_OFFSET,
+ SI_PARAM_VTX4_OFFSET,
+ SI_PARAM_VTX5_OFFSET,
+ SI_PARAM_GS_INSTANCE_ID,
+
+ /* PS only parameters */
+ SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_PRIM_MASK,
+ SI_PARAM_PERSP_SAMPLE,
+ SI_PARAM_PERSP_CENTER,
+ SI_PARAM_PERSP_CENTROID,
+ SI_PARAM_PERSP_PULL_MODEL,
+ SI_PARAM_LINEAR_SAMPLE,
+ SI_PARAM_LINEAR_CENTER,
+ SI_PARAM_LINEAR_CENTROID,
+ SI_PARAM_LINE_STIPPLE_TEX,
+ SI_PARAM_POS_X_FLOAT,
+ SI_PARAM_POS_Y_FLOAT,
+ SI_PARAM_POS_Z_FLOAT,
+ SI_PARAM_POS_W_FLOAT,
+ SI_PARAM_FRONT_FACE,
+ SI_PARAM_ANCILLARY,
+ SI_PARAM_SAMPLE_COVERAGE,
+ SI_PARAM_POS_FIXED_PT,
+
+ SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
+};
struct si_shader;
--
2.5.0
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