[Mesa-dev] [PATCH v2 09/12] radeonsi: Add CE uploader.

[Bas Nieuwenhuizen]

Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++++++++++++++++++++++
 src/gallium/drivers/radeonsi/si_pipe.c        | 11 +++++++++++
 src/gallium/drivers/radeonsi/si_pipe.h        |  3 +++
 3 files changed, 37 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index a937973..0b44ecf 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -61,6 +61,7 @@
 #include "sid.h"
 
 #include "util/u_memory.h"
+#include "util/u_suballoc.h"
 #include "util/u_upload_mgr.h"
 
 
@@ -130,6 +131,28 @@ static void si_release_descriptors(struct si_descriptors *desc)
 	FREE(desc->list);
 }
 
+static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
+			 unsigned *out_offset, struct r600_resource **out_buf) {
+	uint64_t va;
+
+	u_suballocator_alloc(sctx->ce_suballocator, size, out_offset,
+			     (struct pipe_resource**)out_buf);
+	if (!out_buf)
+			return false;
+
+	va = (*out_buf)->gpu_address + *out_offset;
+
+	radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
+	radeon_emit(sctx->ce_ib, ce_offset);
+	radeon_emit(sctx->ce_ib, size / 4);
+	radeon_emit(sctx->ce_ib, va);
+	radeon_emit(sctx->ce_ib, va >> 32);
+
+	sctx->ce_need_synchronization = true;
+	return true;
+}
+
+
 static bool si_upload_descriptors(struct si_context *sctx,
 				  struct si_descriptors *desc)
 {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index ceacf37..b956cda 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -29,6 +29,7 @@
 #include "radeon/radeon_llvm_emit.h"
 #include "radeon/radeon_uvd.h"
 #include "util/u_memory.h"
+#include "util/u_suballoc.h"
 #include "vl/vl_decoder.h"
 
 /*
@@ -41,6 +42,9 @@ static void si_destroy_context(struct pipe_context *context)
 
 	si_release_all_descriptors(sctx);
 
+	if (sctx->ce_suballocator)
+		u_suballocator_destroy(sctx->ce_suballocator);
+
 	pipe_resource_reference(&sctx->esgs_ring, NULL);
 	pipe_resource_reference(&sctx->gsvs_ring, NULL);
 	pipe_resource_reference(&sctx->tf_ring, NULL);
@@ -152,6 +156,13 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
 			sctx->ce_preamble_ib =
 			           ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 		}
+
+		sctx->ce_suballocator =
+				u_suballocator_create(&sctx->b.b, 1024 * 1024,
+						      64, PIPE_BIND_CUSTOM,
+						      PIPE_USAGE_DEFAULT, FALSE);
+		if (!sctx->ce_suballocator)
+			goto fail;
 	}
 
 	sctx->b.gfx.flush = si_context_gfx_flush;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index b3f5ed5..1540c7f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -80,6 +80,7 @@
 
 struct si_compute;
 struct hash_table;
+struct u_suballocator;
 
 struct si_screen {
 	struct r600_common_screen	b;
@@ -191,9 +192,11 @@ struct si_context {
 	void				*custom_blend_dcc_decompress;
 	void				*pstipple_sampler_state;
 	struct si_screen		*screen;
+
 	struct radeon_winsys_cs		*ce_ib;
 	struct radeon_winsys_cs		*ce_preamble_ib;
 	bool				ce_need_synchronization;
+	struct u_suballocator		*ce_suballocator;
 
 	struct pipe_fence_handle	*last_gfx_fence;
 	struct si_shader_ctx_state	fixed_func_tcs_shader;
-- 
2.8.0