[Mesa-dev] [PATCH 1/9] i965: Use offset instead of index in brw_store_register_mem64
Jordan Justen
jordan.l.justen at intel.com
Fri Apr 22 05:18:41 UTC 2016
This matches the byte based offset of brw_load_register_mem*.
The function is also move into intel_batchbuffer.c like
brw_load_register_mem*.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
.../drivers/dri/i965/brw_performance_monitor.c | 5 ++---
src/mesa/drivers/dri/i965/gen6_queryobj.c | 24 +++++++++++++---------
src/mesa/drivers/dri/i965/gen7_sol_state.c | 3 ++-
4 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 1d3d5b2..28c5989 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1431,7 +1431,7 @@ void gen6_init_queryobj_functions(struct dd_function_table *functions);
void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
void brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, int idx);
+ drm_intel_bo *bo, uint32_t reg, uint32_t offset);
/** brw_conditional_render.c */
void brw_init_conditional_render_functions(struct dd_function_table *functions);
diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
index 7e90e8a..a91c6e2 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
@@ -574,10 +574,9 @@ monitor_needs_statistics_registers(struct brw_context *brw,
static void
snapshot_statistics_registers(struct brw_context *brw,
struct brw_perf_monitor_object *monitor,
- uint32_t offset_in_bytes)
+ uint32_t offset)
{
struct gl_context *ctx = &brw->ctx;
- const int offset = offset_in_bytes / sizeof(uint64_t);
const int group = PIPELINE_STATS_COUNTERS;
const int num_counters = ctx->PerfMonitor.Groups[group].NumCounters;
@@ -590,7 +589,7 @@ snapshot_statistics_registers(struct brw_context *brw,
brw_store_register_mem64(brw, monitor->pipeline_stats_bo,
brw->perfmon.statistics_registers[i],
- offset + i);
+ offset + i * sizeof(uint64_t));
}
}
}
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index d508c4c..e788de5 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -50,7 +50,7 @@
*/
void
brw_store_register_mem64(struct brw_context *brw,
- drm_intel_bo *bo, uint32_t reg, int idx)
+ drm_intel_bo *bo, uint32_t reg, uint32_t offset)
{
assert(brw->gen >= 6);
@@ -62,22 +62,22 @@ brw_store_register_mem64(struct brw_context *brw,
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- idx * sizeof(uint64_t));
+ offset);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- sizeof(uint32_t) + idx * sizeof(uint64_t));
+ offset + sizeof(uint32_t));
ADVANCE_BATCH();
} else {
BEGIN_BATCH(6);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- idx * sizeof(uint64_t));
+ offset);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- sizeof(uint32_t) + idx * sizeof(uint64_t));
+ offset + sizeof(uint32_t));
ADVANCE_BATCH();
}
}
@@ -90,9 +90,11 @@ write_primitives_generated(struct brw_context *brw,
if (brw->gen >= 7 && stream > 0) {
brw_store_register_mem64(brw, query_bo,
- GEN7_SO_PRIM_STORAGE_NEEDED(stream), idx);
+ GEN7_SO_PRIM_STORAGE_NEEDED(stream),
+ idx * sizeof(uint64_t));
} else {
- brw_store_register_mem64(brw, query_bo, CL_INVOCATION_COUNT, idx);
+ brw_store_register_mem64(brw, query_bo, CL_INVOCATION_COUNT,
+ idx * sizeof(uint64_t));
}
}
@@ -103,9 +105,11 @@ write_xfb_primitives_written(struct brw_context *brw,
brw_emit_mi_flush(brw);
if (brw->gen >= 7) {
- brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream), idx);
+ brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream),
+ idx * sizeof(uint64_t));
} else {
- brw_store_register_mem64(brw, bo, GEN6_SO_NUM_PRIMS_WRITTEN, idx);
+ brw_store_register_mem64(brw, bo, GEN6_SO_NUM_PRIMS_WRITTEN,
+ idx * sizeof(uint64_t));
}
}
@@ -159,7 +163,7 @@ emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo,
*/
brw_emit_mi_flush(brw);
- brw_store_register_mem64(brw, bo, reg, idx);
+ brw_store_register_mem64(brw, bo, reg, idx * sizeof(uint64_t));
}
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index c44572c..d4ca1ec 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -369,9 +369,10 @@ gen7_save_primitives_written_counters(struct brw_context *brw,
/* Emit MI_STORE_REGISTER_MEM commands to write the values. */
for (int i = 0; i < streams; i++) {
+ int offset = (obj->prim_count_buffer_index + i) * sizeof(uint64_t);
brw_store_register_mem64(brw, obj->prim_count_bo,
GEN7_SO_NUM_PRIMS_WRITTEN(i),
- obj->prim_count_buffer_index + i);
+ offset);
}
/* Update where to write data to. */
--
2.8.0.rc3
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