[Mesa-dev] [PATCH 5/9] i965/gen6+: Add support for storing immediate data into a buffer

[Jordan Justen]

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h       |  4 +++
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 45 +++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/intel_reg.h         |  1 +
 3 files changed, 50 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 3fd3cb3..c4fe02c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1450,6 +1450,10 @@ void brw_store_register_mem32(struct brw_context *brw,
                               drm_intel_bo *bo, uint32_t reg, uint32_t offset);
 void brw_store_register_mem64(struct brw_context *brw,
                               drm_intel_bo *bo, uint32_t reg, uint32_t offset);
+void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+                          uint32_t offset, uint32_t imm);
+void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+                          uint32_t offset, uint64_t imm);
 
 /*======================================================================
  * brw_state_dump.c
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 03a31b6..334be0c 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -600,3 +600,48 @@ brw_store_register_mem64(struct brw_context *brw,
       ADVANCE_BATCH();
    }
 }
+
+/*
+ * Write 32-bits of immediate data to a GPU memory buffer.
+ */
+void
+brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
+                     uint32_t offset, uint32_t imm)
+{
+   const int len = brw->gen >= 8 ? 4 : 3;
+   assert(brw->gen >= 6);
+
+   BEGIN_BATCH(len);
+   OUT_BATCH(MI_STORE_DATA_IMM | (len - 2));
+   if (len > 3)
+      OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                  offset);
+   else
+      OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                offset);
+   OUT_BATCH(imm);
+   ADVANCE_BATCH();
+}
+
+/*
+ * Write 64-bits of immediate data to a GPU memory buffer.
+ */
+void
+brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,
+                     uint32_t offset, uint64_t imm)
+{
+   const int len = brw->gen >= 8 ? 5 : 4;
+   assert(brw->gen >= 6);
+
+   BEGIN_BATCH(len);
+   OUT_BATCH(MI_STORE_DATA_IMM | (len - 2));
+   if (len > 4)
+      OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                  offset);
+   else
+      OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
+                offset);
+   OUT_BATCH(imm & 0xffffffffu);
+   OUT_BATCH(imm >> 32);
+   ADVANCE_BATCH();
+}
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
index 01b4358..c0d2874 100644
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@ -35,6 +35,7 @@
 #define FLUSH_MAP_CACHE				(1 << 0)
 #define INHIBIT_FLUSH_RENDER_CACHE		(1 << 2)
 
+#define MI_STORE_DATA_IMM		(CMD_MI | (0x20 << 23))
 #define MI_LOAD_REGISTER_IMM		(CMD_MI | (0x22 << 23))
 
 #define MI_FLUSH_DW			(CMD_MI | (0x26 << 23) | 2)
-- 
2.8.0.rc3