[Mesa-dev] [PATCH 36/40] i965/blorp: Reconfigure base state address only if needed

[Kenneth Graunke]

On Saturday, April 16, 2016 4:43:04 PM PDT Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.cpp  | 3 ++-
>  src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 +++++
>  src/mesa/drivers/dri/i965/gen8_blorp.cpp | 4 +++-
>  3 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/
i965/brw_blorp.cpp
> index ce09b09..1d3b3e2 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
> @@ -284,7 +284,8 @@ retry:
>     if (unlikely(brw->always_flush_batch))
>        intel_batchbuffer_flush(brw);
>  
> -   const uint64_t do_not_smash_bits = BRW_NEW_URB_SIZE;
> +   const uint64_t do_not_smash_bits = BRW_NEW_URB_SIZE |
> +                                      BRW_NEW_STATE_BASE_ADDRESS;

This patch looks safe to me.  It might be worth also adding
BRW_NEW_PROGRAM_CACHE to do_not_smash_bits.  Otherwise, the first
ordinary draw after BLORP will have to re-emit STATE_BASE_ADDRESS,
and that shouldn't normally be necessary, either.

As is,
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

A patch to implement my suggestion would also get an R-b.

>     /* We've smashed all state compared to what the normal 3D pipeline
>      * rendering tracks for GL.
> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/
dri/i965/gen6_blorp.cpp
> index b741e19..a1b254d 100644
> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> @@ -49,6 +49,9 @@ gen6_blorp_emit_state_base_address(struct brw_context 
*brw,
>  {
>     uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
>  
> +   if (!(brw_state_base_address.dirty.brw & brw->ctx.NewDriverState))
> +      return;
> +
>     BEGIN_BATCH(10);
>     OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
>     OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
> @@ -77,6 +80,8 @@ gen6_blorp_emit_state_base_address(struct brw_context 
*brw,
>     OUT_BATCH(1); /* IndirectObjectUpperBound*/
>     OUT_BATCH(1); /* InstructionAccessUpperBound */
>     ADVANCE_BATCH();
> +
> +   brw->ctx.NewDriverState |= BRW_NEW_STATE_BASE_ADDRESS;
>  }
>  
>  static void
> diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.cpp b/src/mesa/drivers/
dri/i965/gen8_blorp.cpp
> index 4ce32c3..cd02b70 100644
> --- a/src/mesa/drivers/dri/i965/gen8_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen8_blorp.cpp
> @@ -635,7 +635,9 @@ gen8_blorp_exec(struct brw_context *brw, const 
brw_blorp_params *params)
>  
>     uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
>  
> -   gen8_upload_state_base_address(brw);
> +   if (gen8_state_base_address.dirty.brw & brw->ctx.NewDriverState)
> +      gen8_upload_state_base_address(brw);
> +
>     gen7_blorp_emit_cc_viewport(brw);
>     gen7_l3_state.emit(brw);
>  
> 

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