[Mesa-dev] [PATCH] i965: Fix the render ring prelude on Gen4-5.

[Kenneth Graunke]

My intention was to have the render ring prelude occur at the first
point where we start emiting render commands into a batch.

Gen4-5 have a single ring that handles both BLT and 3D commands, so it's
possible to have a BLT -> RENDER transition in the middle of a batch
(not just at the start when prev_ring == UNKNOWN).  We want to call the
prelude here as well.

Today, this means we'll miss a OA bookend snapshot.  Topi's also
thinking of moving some code here that absolutely must run before RENDER
commands happen, at which point fixing this will be more critical.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index e41f927..47a2864 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -128,7 +128,7 @@ intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
     */
    brw->batch.ring = ring;
 
-   if (unlikely(prev_ring == UNKNOWN_RING && ring == RENDER_RING))
+   if (unlikely(prev_ring != RENDER_RING && ring == RENDER_RING))
       intel_batchbuffer_emit_render_ring_prelude(brw);
 }
 
-- 
2.8.0