[Mesa-dev] [PATCH 16/95] i965/vec4: We only support 32-bit integer ALU operations for now
Francisco Jerez
currojerez at riseup.net
Wed Aug 3 00:56:33 UTC 2016
Iago Toral Quiroga <itoral at igalia.com> writes:
> Add asserts so we remember to address this when we enable 64-bit
> integer support, as suggested by Connor and Jason.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 70 ++++++++++++++++++++++--------
> 1 file changed, 52 insertions(+), 18 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 1d33fb2..25fd1fe 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -1083,9 +1083,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
> }
>
> - case nir_op_fadd:
> - /* fall through */
> case nir_op_iadd:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + case nir_op_fadd:
> inst = emit(ADD(dst, op[0], op[1]));
> inst->saturate = instr->dest.saturate;
> break;
> @@ -1096,6 +1096,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_imul: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> if (devinfo->gen < 8) {
> nir_const_value *value0 = nir_src_as_const_value(instr->src[0].src);
> nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
> @@ -1131,6 +1132,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>
> case nir_op_imul_high:
> case nir_op_umul_high: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
>
> if (devinfo->gen >= 8)
> @@ -1169,6 +1171,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>
> case nir_op_idiv:
> case nir_op_udiv:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit_math(SHADER_OPCODE_INT_QUOTIENT, dst, op[0], op[1]);
> break;
>
> @@ -1178,6 +1181,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> * appears that our hardware just does the right thing for signed
> * remainder.
> */
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]);
> break;
>
> @@ -1231,6 +1235,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_uadd_carry: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
>
> emit(ADDC(dst_null_ud(), op[0], op[1]));
> @@ -1239,6 +1244,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> }
>
> case nir_op_usub_borrow: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
>
> emit(SUBB(dst_null_ud(), op[0], op[1]));
> @@ -1306,16 +1312,18 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
> }
>
> - case nir_op_fmin:
> case nir_op_imin:
> case nir_op_umin:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + case nir_op_fmin:
> inst = emit_minmax(BRW_CONDITIONAL_L, dst, op[0], op[1]);
> inst->saturate = instr->dest.saturate;
> break;
>
> - case nir_op_fmax:
> case nir_op_imax:
> case nir_op_umax:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + case nir_op_fmax:
> inst = emit_minmax(BRW_CONDITIONAL_GE, dst, op[0], op[1]);
> inst->saturate = instr->dest.saturate;
> break;
> @@ -1328,26 +1336,30 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> case nir_op_fddy_fine:
> unreachable("derivatives are not valid in vertex shaders");
>
> - case nir_op_flt:
> case nir_op_ilt:
> case nir_op_ult:
> - case nir_op_fge:
> case nir_op_ige:
> case nir_op_uge:
> - case nir_op_feq:
> case nir_op_ieq:
> - case nir_op_fne:
> case nir_op_ine:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + /* Fallthrough */
> + case nir_op_flt:
> + case nir_op_fge:
> + case nir_op_feq:
> + case nir_op_fne:
> emit(CMP(dst, op[0], op[1],
> brw_conditional_for_nir_comparison(instr->op)));
> break;
>
> - case nir_op_ball_fequal2:
> case nir_op_ball_iequal2:
> - case nir_op_ball_fequal3:
> case nir_op_ball_iequal3:
> - case nir_op_ball_fequal4:
> - case nir_op_ball_iequal4: {
> + case nir_op_ball_iequal4:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + /* Fallthrough */
> + case nir_op_ball_fequal2:
> + case nir_op_ball_fequal3:
> + case nir_op_ball_fequal4: {
> unsigned swiz =
> brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
>
> @@ -1359,12 +1371,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
> }
>
> - case nir_op_bany_fnequal2:
> case nir_op_bany_inequal2:
> - case nir_op_bany_fnequal3:
> case nir_op_bany_inequal3:
> - case nir_op_bany_fnequal4:
> - case nir_op_bany_inequal4: {
> + case nir_op_bany_inequal4:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + /* Fallthrough */
> + case nir_op_bany_fnequal2:
> + case nir_op_bany_fnequal3:
> + case nir_op_bany_fnequal4: {
> unsigned swiz =
> brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
>
> @@ -1378,6 +1392,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> }
>
> case nir_op_inot:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> if (devinfo->gen >= 8) {
> op[0] = resolve_source_modifiers(op[0]);
> }
> @@ -1385,6 +1400,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_ixor:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> if (devinfo->gen >= 8) {
> op[0] = resolve_source_modifiers(op[0]);
> op[1] = resolve_source_modifiers(op[1]);
> @@ -1393,6 +1409,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_ior:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> if (devinfo->gen >= 8) {
> op[0] = resolve_source_modifiers(op[0]);
> op[1] = resolve_source_modifiers(op[1]);
> @@ -1401,6 +1418,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_iand:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> if (devinfo->gen >= 8) {
> op[0] = resolve_source_modifiers(op[0]);
> op[1] = resolve_source_modifiers(op[1]);
> @@ -1486,31 +1504,38 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_unpack_unorm_4x8:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit_unpack_unorm_4x8(dst, op[0]);
> break;
>
> case nir_op_pack_unorm_4x8:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit_pack_unorm_4x8(dst, op[0]);
> break;
>
> case nir_op_unpack_snorm_4x8:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit_unpack_snorm_4x8(dst, op[0]);
> break;
>
> case nir_op_pack_snorm_4x8:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit_pack_snorm_4x8(dst, op[0]);
> break;
>
> case nir_op_bitfield_reverse:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(BFREV(dst, op[0]));
> break;
>
> case nir_op_bit_count:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(CBIT(dst, op[0]));
> break;
>
> case nir_op_ufind_msb:
> case nir_op_ifind_msb: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(FBH(retype(dst, BRW_REGISTER_TYPE_UD), op[0]));
>
> /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
> @@ -1527,6 +1552,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> }
>
> case nir_op_find_lsb:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(FBL(dst, op[0]));
> break;
>
> @@ -1535,6 +1561,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> unreachable("should have been lowered");
> case nir_op_ubfe:
> case nir_op_ibfe:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> op[0] = fix_3src_operand(op[0]);
> op[1] = fix_3src_operand(op[1]);
> op[2] = fix_3src_operand(op[2]);
> @@ -1543,10 +1570,12 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_bfm:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(BFI1(dst, op[0], op[1]));
> break;
>
> case nir_op_bfi:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> op[0] = fix_3src_operand(op[0]);
> op[1] = fix_3src_operand(op[1]);
> op[2] = fix_3src_operand(op[2]);
> @@ -1584,6 +1613,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> * -> non-negative val generates 0x00000000.
> * Predicated OR sets 1 if val is positive.
> */
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_G));
> emit(ASR(dst, op[0], brw_imm_d(31)));
> inst = emit(OR(dst, src_reg(dst), brw_imm_d(1)));
> @@ -1591,14 +1621,17 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> break;
>
> case nir_op_ishl:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(SHL(dst, op[0], op[1]));
> break;
>
> case nir_op_ishr:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(ASR(dst, op[0], op[1]));
> break;
>
> case nir_op_ushr:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> emit(SHR(dst, op[0], op[1]));
> break;
>
> @@ -1662,10 +1695,11 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> inst->saturate = instr->dest.saturate;
> break;
>
> - case nir_op_fabs:
> case nir_op_iabs:
> - case nir_op_fneg:
> case nir_op_ineg:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + case nir_op_fabs:
> + case nir_op_fneg:
> case nir_op_fsat:
> unreachable("not reached: should be lowered by lower_source mods");
>
> --
> 2.7.4
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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