[Mesa-dev] [PATCH] anv/gen7_pipeline: Set PixelShaderKillPixel when needed

[Jason Ekstrand]

Drp... There's more work to do here to get the behavior 100% correct on
gen7 but this fixes a bug and is a step in the right direction.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

Unfortunately, gen7 is a bit crazy so the simple solution doesn't cover all
the cases.  For the full fix take a look at

https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/gen7_wm_state.c#n74

and

https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/gen7_wm_state.c#n81

and maybe

https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/gen7_wm_state.c#n119

--Jason

On Aug 4, 2016 4:45 PM, "Nanley Chery" <nanleychery at gmail.com> wrote:

> According to the IVB PRM Vol2 P1, this bit must be set if a pixel shader
> contains a discard instruction.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97207
> Cc: "12.0" <mesa-stable at lists.freedesktop.org>
> Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
> ---
>  src/intel/vulkan/gen7_pipeline.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_
> pipeline.c
> index 8ce50be..d1b18e0 100644
> --- a/src/intel/vulkan/gen7_pipeline.c
> +++ b/src/intel/vulkan/gen7_pipeline.c
> @@ -297,6 +297,7 @@ genX(graphics_pipeline_create)(
>           wm.LineEndCapAntialiasingRegionWidth   = 0; /* 0.5 pixels */
>           wm.LineAntialiasingRegionWidth         = 1; /* 1.0 pixels */
>           wm.PointRasterizationRule              = RASTRULE_UPPER_RIGHT;
> +         wm.PixelShaderKillPixel                = wm_prog_data->uses_kill;
>           wm.PixelShaderComputedDepthMode        =
> wm_prog_data->computed_depth_mode;
>           wm.PixelShaderUsesSourceDepth          =
> wm_prog_data->uses_src_depth;
>           wm.PixelShaderUsesSourceW              =
> wm_prog_data->uses_src_w;
> --
> 2.9.0
>
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