[Mesa-dev] [PATCH 3/3] nir: Define system values for vc4's blending-lowering arguments.
Eric Anholt
eric at anholt.net
Sat Aug 6 07:28:38 UTC 2016
In the GLSL-to-NIR conversion of VC4, I had a bit of trouble with what I
was calling the "state uniforms" that I was putting into the NIR fighting
with its other lowering passes. Instead of using magic uniform base
numbers in the backend, follow the lead of load_user_clip_plane and just
define system values for them.
---
src/compiler/nir/nir_intrinsics.h | 11 +++++-
src/gallium/drivers/vc4/vc4_nir_lower_blend.c | 29 ++++++++------
src/gallium/drivers/vc4/vc4_nir_lower_io.c | 8 ++--
src/gallium/drivers/vc4/vc4_program.c | 56 +++++++++++++++------------
src/gallium/drivers/vc4/vc4_qir.h | 7 ----
5 files changed, 64 insertions(+), 47 deletions(-)
diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h
index 4cb04373e00d..f9dea10a6917 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -309,7 +309,16 @@ SYSTEM_VALUE(work_group_id, 3, 0, xx, xx, xx)
SYSTEM_VALUE(user_clip_plane, 4, 1, UCP_ID, xx, xx)
SYSTEM_VALUE(num_work_groups, 3, 0, xx, xx, xx)
SYSTEM_VALUE(helper_invocation, 1, 0, xx, xx, xx)
-SYSTEM_VALUE(channel_num, 1, 0, xx, xx, xx)
+SYSTEM_VALUE(channel_num, 1, 0, BASE, xx, xx)
+SYSTEM_VALUE(alpha_ref_float, 1, 0, xx, xx, xx)
+
+/* Blend constant color values. Float values are clamped. */
+SYSTEM_VALUE(blend_const_color_r_float, 1, 1, xx, xx, xx)
+SYSTEM_VALUE(blend_const_color_g_float, 1, 0, xx, xx, xx)
+SYSTEM_VALUE(blend_const_color_b_float, 1, 0, xx, xx, xx)
+SYSTEM_VALUE(blend_const_color_a_float, 1, 0, xx, xx, xx)
+SYSTEM_VALUE(blend_const_color_rgba8888_unorm, 1, 0, xx, xx, xx)
+SYSTEM_VALUE(blend_const_color_aaaa8888_unorm, 1, 0, xx, xx, xx)
/**
* Barycentric coordinate intrinsics.
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
index 93a3572f0369..f70821862cf0 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
@@ -127,9 +127,12 @@ vc4_blend_channel_f(nir_builder *b,
return nir_imm_float(b, 1.0);
}
case PIPE_BLENDFACTOR_CONST_COLOR:
- return vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_X + channel);
+ return nir_load_system_value(b,
+ nir_intrinsic_load_blend_const_color_r_float +
+ channel,
+ 0);
case PIPE_BLENDFACTOR_CONST_ALPHA:
- return vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_W);
+ return nir_load_blend_const_color_a_float(b);
case PIPE_BLENDFACTOR_ZERO:
return nir_imm_float(b, 0.0);
case PIPE_BLENDFACTOR_INV_SRC_COLOR:
@@ -142,10 +145,13 @@ vc4_blend_channel_f(nir_builder *b,
return nir_fsub(b, nir_imm_float(b, 1.0), dst[channel]);
case PIPE_BLENDFACTOR_INV_CONST_COLOR:
return nir_fsub(b, nir_imm_float(b, 1.0),
- vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_X + channel));
+ nir_load_system_value(b,
+ nir_intrinsic_load_blend_const_color_r_float +
+ channel,
+ 0));
case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
return nir_fsub(b, nir_imm_float(b, 1.0),
- vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_W));
+ nir_load_blend_const_color_a_float(b));
default:
case PIPE_BLENDFACTOR_SRC1_COLOR:
@@ -196,9 +202,9 @@ vc4_blend_channel_i(nir_builder *b,
nir_imm_int(b, ~0),
a_chan);
case PIPE_BLENDFACTOR_CONST_COLOR:
- return vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_RGBA);
+ return nir_load_blend_const_color_rgba8888_unorm(b);
case PIPE_BLENDFACTOR_CONST_ALPHA:
- return vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_AAAA);
+ return nir_load_blend_const_color_aaaa8888_unorm(b);
case PIPE_BLENDFACTOR_ZERO:
return nir_imm_int(b, 0);
case PIPE_BLENDFACTOR_INV_SRC_COLOR:
@@ -210,9 +216,11 @@ vc4_blend_channel_i(nir_builder *b,
case PIPE_BLENDFACTOR_INV_DST_COLOR:
return nir_inot(b, dst);
case PIPE_BLENDFACTOR_INV_CONST_COLOR:
- return nir_inot(b, vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_RGBA));
+ return nir_inot(b,
+ nir_load_blend_const_color_rgba8888_unorm(b));
case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
- return nir_inot(b, vc4_nir_get_state_uniform(b, QUNIFORM_BLEND_CONST_COLOR_AAAA));
+ return nir_inot(b,
+ nir_load_blend_const_color_aaaa8888_unorm(b));
default:
case PIPE_BLENDFACTOR_SRC1_COLOR:
@@ -475,11 +483,10 @@ vc4_nir_emit_alpha_test_discard(struct vc4_compile *c, nir_builder *b,
if (!c->fs_key->alpha_test)
return;
- nir_ssa_def *alpha_ref =
- vc4_nir_get_state_uniform(b, QUNIFORM_ALPHA_REF);
nir_ssa_def *condition =
vc4_nir_pipe_compare_func(b, c->fs_key->alpha_test_func,
- alpha, alpha_ref);
+ alpha,
+ nir_load_alpha_ref_float(b));
nir_intrinsic_instr *discard =
nir_intrinsic_instr_create(b->shader,
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_io.c b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
index 3d08b6481258..d61c95a6b5db 100644
--- a/src/gallium/drivers/vc4/vc4_nir_lower_io.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_io.c
@@ -342,11 +342,13 @@ vc4_nir_lower_uniform(struct vc4_compile *c, nir_builder *b,
intr_comp->num_components = 1;
nir_ssa_dest_init(&intr_comp->instr, &intr_comp->dest, 1, 32, NULL);
- /* Convert the uniform offset to bytes. If it happens to be a
- * constant, constant-folding will clean up the shift for us.
+ /* Convert the uniform offset to bytes. If it happens
+ * to be a constant, constant-folding will clean up
+ * the shift for us.
*/
nir_intrinsic_set_base(intr_comp,
- nir_intrinsic_base(intr) * 16 + i * 4);
+ nir_intrinsic_base(intr) * 16 +
+ i * 4);
intr_comp->src[0] =
nir_src_for_ssa(nir_ishl(b, intr->src[0].ssa,
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index f368ea07bf6e..6f57e1108059 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -110,21 +110,6 @@ indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
return qir_TEX_RESULT(c);
}
-nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
- enum quniform_contents contents)
-{
- nir_intrinsic_instr *intr =
- nir_intrinsic_instr_create(b->shader,
- nir_intrinsic_load_uniform);
- nir_intrinsic_set_base(intr,
- (VC4_NIR_STATE_UNIFORM_OFFSET + contents) * 4);
- intr->num_components = 1;
- intr->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
- nir_ssa_dest_init(&intr->instr, &intr->dest, 1, 32, NULL);
- nir_builder_instr_insert(b, &intr->instr);
- return &intr->dest.ssa;
-}
-
nir_ssa_def *
vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
{
@@ -1567,16 +1552,9 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
assert(offset % 4 == 0);
/* We need dwords */
offset = offset / 4;
- if (offset < VC4_NIR_STATE_UNIFORM_OFFSET) {
- ntq_store_dest(c, &instr->dest, 0,
- qir_uniform(c, QUNIFORM_UNIFORM,
- offset));
- } else {
- ntq_store_dest(c, &instr->dest, 0,
- qir_uniform(c, offset -
- VC4_NIR_STATE_UNIFORM_OFFSET,
- 0));
- }
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_UNIFORM,
+ offset));
} else {
ntq_store_dest(c, &instr->dest, 0,
indirect_uniform_load(c, instr));
@@ -1592,6 +1570,34 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
}
break;
+ case nir_intrinsic_load_blend_const_color_r_float:
+ case nir_intrinsic_load_blend_const_color_g_float:
+ case nir_intrinsic_load_blend_const_color_b_float:
+ case nir_intrinsic_load_blend_const_color_a_float:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
+ (instr->intrinsic -
+ nir_intrinsic_load_blend_const_color_r_float),
+ 0));
+ break;
+
+ case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
+ 0));
+ break;
+
+ case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
+ 0));
+ break;
+
+ case nir_intrinsic_load_alpha_ref_float:
+ ntq_store_dest(c, &instr->dest, 0,
+ qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
+ break;
+
case nir_intrinsic_load_sample_mask_in:
ntq_store_dest(c, &instr->dest, 0,
qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
diff --git a/src/gallium/drivers/vc4/vc4_qir.h b/src/gallium/drivers/vc4/vc4_qir.h
index e6297c5c82ce..12b081bc6ab3 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -505,11 +505,6 @@ struct vc4_compile {
#define VC4_NIR_MS_MASK_OUTPUT 2000000000
-/* Special offset for nir_load_uniform values to get a QUNIFORM_*
- * state-dependent value.
- */
-#define VC4_NIR_STATE_UNIFORM_OFFSET 1000000000
-
struct vc4_compile *qir_compile_init(void);
void qir_compile_destroy(struct vc4_compile *c);
struct qblock *qir_new_block(struct vc4_compile *c);
@@ -566,8 +561,6 @@ bool qir_opt_small_immediates(struct vc4_compile *c);
bool qir_opt_vpm(struct vc4_compile *c);
void vc4_nir_lower_blend(nir_shader *s, struct vc4_compile *c);
void vc4_nir_lower_io(nir_shader *s, struct vc4_compile *c);
-nir_ssa_def *vc4_nir_get_state_uniform(struct nir_builder *b,
- enum quniform_contents contents);
nir_ssa_def *vc4_nir_get_swizzled_channel(struct nir_builder *b,
nir_ssa_def **srcs, int swiz);
void vc4_nir_lower_txf_ms(nir_shader *s, struct vc4_compile *c);
--
2.8.1
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