[Mesa-dev] [PATCH 4/7] anv/pipeline/gen8: Unconditionally set DXMultisampleRasterizaitonEnable

[Jason Ekstrand]

On Sat, Aug 6, 2016 at 4:55 PM, Jason Ekstrand <jason at jlekstrand.net> wrote:

> On Sat, Aug 6, 2016 at 4:15 PM, Kenneth Graunke <kenneth at whitecape.org>
> wrote:
>
>> On Saturday, August 6, 2016 10:31:19 AM PDT Jason Ekstrand wrote:
>> > This bit doesn't enable multisampling, it simply sets the multisampling
>> > mode to DX which is what we want.
>>
>> This in fact does not set the multisampling API mode.  That's the
>> DXMultisampleRasterizationMode field, while you're changing the
>> DXMultisampleRasterizationEnable bit.
>>
>> I'm not saying this is wrong, but could you provide a better explanation
>> for this change?  I think you need to cite the 3DSTATE_INT Multisample
>> Rasterization Modes table and why the signals ultimately produced work
>> out to what we want despite changing this.
>>
>
> I just kicked this guy off to CI:
>
> https://cgit.freedesktop.org/~jekstrand/mesa/commit/?h=jenkins_gl
>
> the i965 driver is probably a better place to prototype this change anyway
> since it is getting better test coverage.
>

Jenkins wasn't too happy with that patch but it seems to only be a problem
when multisampling is disabled on a multisampled buffer.  Since Vulkan has
no concept of non-multisampled buffers with > 1 sample (Hooray non-stupid
API's!) I think we're fine.


>
>
>> If this works, it would be nice - in the GL driver, we could likely
>> drop the _NEW_MULTISAMPLE flag in the 3DSTATE_RASTER atom.
>>
>> > ---
>> >  src/intel/vulkan/gen8_pipeline.c | 11 ++---------
>> >  1 file changed, 2 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/src/intel/vulkan/gen8_pipeline.c
>> b/src/intel/vulkan/gen8_pipeline.c
>> > index 6b7936a..ad8a643 100644
>> > --- a/src/intel/vulkan/gen8_pipeline.c
>> > +++ b/src/intel/vulkan/gen8_pipeline.c
>> > @@ -47,14 +47,8 @@ emit_ia_state(struct anv_pipeline *pipeline,
>> >  static void
>> >  emit_rs_state(struct anv_pipeline *pipeline,
>> >                const VkPipelineRasterizationStateCreateInfo *info,
>> > -              const VkPipelineMultisampleStateCreateInfo *ms_info,
>> >                const struct anv_graphics_pipeline_create_info *extra)
>> >  {
>> > -   uint32_t samples = 1;
>> > -
>> > -   if (ms_info)
>> > -      samples = ms_info->rasterizationSamples;
>> > -
>> >     struct GENX(3DSTATE_SF) sf = {
>> >        GENX(3DSTATE_SF_header),
>> >     };
>> > @@ -75,7 +69,7 @@ emit_rs_state(struct anv_pipeline *pipeline,
>> >     /* For details on 3DSTATE_RASTER multisample state, see the BSpec
>> table
>> >      * "Multisample Modes State".
>> >      */
>> > -   raster.DXMultisampleRasterizationEnable = samples > 1;
>> > +   raster.DXMultisampleRasterizationEnable = true;
>> >     raster.ForcedSampleCount = FSC_NUMRASTSAMPLES_0;
>> >     raster.ForceMultisampling = false;
>> >
>> > @@ -176,8 +170,7 @@ genX(graphics_pipeline_create)(
>> >     assert(pCreateInfo->pInputAssemblyState);
>> >     emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
>> >     assert(pCreateInfo->pRasterizationState);
>> > -   emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
>> > -                 pCreateInfo->pMultisampleState, extra);
>> > +   emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
>> >     emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
>> >     emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass,
>> subpass);
>> >     emit_cb_state(pipeline, pCreateInfo->pColorBlendState,
>> >
>>
>>
>
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