[Mesa-dev] [PATCH 4/4] i965: Fix barrier count shift in scalar TCS backend.

Alejandro Piñeiro apinheiro at igalia.com
Wed Aug 17 19:31:48 UTC 2016


Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>

On 17/08/16 16:15, Kenneth Graunke wrote:
> The "Barrier Count" field goes in 14:9 of m0.2.  The vec4 backend
> correctly shifts by 9, but the scalar backend only shifted by 8.
> 
> It's not like this changed - I think I just made a typo when writing
> the original scalar TCS backend code.
> 
> Cc: mesa-stable at lists.freedesktop.org
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index bb254d6..1aa57cb 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -2436,7 +2436,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
>  
>        /* Set the Barrier Count and the enable bit */
>        fwa_bld.OR(m0_2, m0_2,
> -                 brw_imm_ud(tcs_prog_data->instances << 8 | (1 << 15)));
> +                 brw_imm_ud(tcs_prog_data->instances << 9 | (1 << 15)));
>  
>        bld.emit(SHADER_OPCODE_BARRIER, bld.null_reg_ud(), m0);
>        break;
> 

-- 
Alejandro Piñeiro <apinheiro at igalia.com>


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