[Mesa-dev] [PATCH 3/4] winsys/amdgpu: disable IB chaining on SI

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index bf3e306..e246f81 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -242,23 +242,24 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 }
 
 /* COMMAND SUBMISSION */
 
 static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
 {
    return cs->request.ip_type != AMDGPU_HW_IP_UVD &&
           cs->request.ip_type != AMDGPU_HW_IP_VCE;
 }
 
-static bool amdgpu_cs_has_chaining(enum ring_type ring_type)
+static bool amdgpu_cs_has_chaining(struct amdgpu_cs *cs)
 {
-   return ring_type == RING_GFX;
+   return cs->ctx->ws->info.chip_class >= CIK &&
+          cs->ring_type == RING_GFX;
 }
 
 static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type)
 {
    if (ring_type == RING_GFX)
       return 4; /* for chaining */
 
    return 0;
 }
 
@@ -377,21 +378,21 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib)
    struct pb_buffer *pb;
    uint8_t *mapped;
    unsigned buffer_size;
 
    /* Always create a buffer that is at least as large as the maximum seen IB
     * size, aligned to a power of two (and multiplied by 4 to reduce internal
     * fragmentation if chaining is not available). Limit to 512k dwords, which
     * is the largest power of two that fits into the size field of the
     * INDIRECT_BUFFER packet.
     */
-   if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib)->ring_type))
+   if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib)))
       buffer_size = 4 *util_next_power_of_two(ib->max_ib_size);
    else
       buffer_size = 4 *util_next_power_of_two(4 * ib->max_ib_size);
 
    buffer_size = MIN2(buffer_size, 4 * 512 * 1024);
 
    switch (ib->ib_type) {
    case IB_CONST_PREAMBLE:
       buffer_size = MAX2(buffer_size, 4 * 1024);
       break;
@@ -470,21 +471,21 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
       ib_size = 8 * 1024 * 4;
       break;
    case IB_MAIN:
       ib = &cs->main;
       ib_size = 4 * 1024 * 4;
       break;
    default:
       unreachable("unhandled IB type");
    }
 
-   if (!amdgpu_cs_has_chaining(cs->ring_type)) {
+   if (!amdgpu_cs_has_chaining(cs)) {
       ib_size = MAX2(ib_size,
                      4 * MIN2(util_next_power_of_two(ib->max_ib_size),
                               amdgpu_ib_max_submit_dwords(ib_type)));
    }
 
    ib->max_ib_size = ib->max_ib_size - ib->max_ib_size / 32;
 
    ib->base.prev_dw = 0;
    ib->base.num_prev = 0;
    ib->base.current.cdw = 0;
@@ -734,21 +735,21 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw)
    assert(rcs->current.cdw <= rcs->current.max_dw);
 
    if (requested_size > amdgpu_ib_max_submit_dwords(ib->ib_type))
       return false;
 
    ib->max_ib_size = MAX2(ib->max_ib_size, requested_size);
 
    if (rcs->current.max_dw - rcs->current.cdw >= dw)
       return true;
 
-   if (!amdgpu_cs_has_chaining(cs->ring_type))
+   if (!amdgpu_cs_has_chaining(cs))
       return false;
 
    /* Allocate a new chunk */
    if (rcs->num_prev >= rcs->max_prev) {
       unsigned new_max_prev = MAX2(1, 2 * rcs->max_prev);
       struct radeon_winsys_cs_chunk *new_prev;
 
       new_prev = REALLOC(rcs->prev,
                          sizeof(*new_prev) * rcs->max_prev,
                          sizeof(*new_prev) * new_max_prev);
-- 
2.7.4