[Mesa-dev] [PATCH 26/31] i965: Roll brw_get_ccs_resolve_rect into blorp_ccs_resolve

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/blorp_clear.c   | 32 ++++++++++++++++++++++++---
 src/mesa/drivers/dri/i965/brw_meta_util.c | 36 -------------------------------
 src/mesa/drivers/dri/i965/brw_meta_util.h |  6 ------
 3 files changed, 29 insertions(+), 45 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/blorp_clear.c b/src/mesa/drivers/dri/i965/blorp_clear.c
index ecb3e08..c91aed9 100644
--- a/src/mesa/drivers/dri/i965/blorp_clear.c
+++ b/src/mesa/drivers/dri/i965/blorp_clear.c
@@ -162,9 +162,35 @@ brw_blorp_ccs_resolve(struct blorp_context *blorp, void *batch,
    brw_blorp_surface_info_init(blorp, &params.dst, surf,
                                0 /* level */, 0 /* layer */, format, true);
 
-   brw_get_ccs_resolve_rect(blorp->isl_dev, &params.dst.aux_surf,
-                            &params.x0, &params.y0,
-                            &params.x1, &params.y1);
+   /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
+    *
+    *     A rectangle primitive must be scaled down by the following factors
+    *     with respect to render target being resolved.
+    *
+    * The scaledown factors in the table that follows are related to the block
+    * size of the CCS format.  For IVB and HSW, we divide by two, for BDW we
+    * multiply by 8 and 16. On Sky Lake, we multiply by 8.
+    */
+   const struct isl_format_layout *aux_fmtl =
+      isl_format_get_layout(params.dst.aux_surf.format);
+   assert(aux_fmtl->txc == ISL_TXC_CCS);
+
+   unsigned x_scaledown, y_scaledown;
+   if (ISL_DEV_GEN(blorp->isl_dev) >= 9) {
+      x_scaledown = aux_fmtl->bw * 8;
+      y_scaledown = aux_fmtl->bh * 8;
+   } else if (ISL_DEV_GEN(blorp->isl_dev) >= 8) {
+      x_scaledown = aux_fmtl->bw * 8;
+      y_scaledown = aux_fmtl->bh * 16;
+   } else {
+      x_scaledown = aux_fmtl->bw / 2;
+      y_scaledown = aux_fmtl->bh / 2;
+   }
+   params.x0 = params.y0 = 0;
+   params.x1 = params.dst.aux_surf.logical_level0_px.width;
+   params.y1 = params.dst.aux_surf.logical_level0_px.height;
+   params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
+   params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
 
    if (blorp->isl_dev->info->gen >= 9) {
       if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c
index bc3a62d..52b7be4 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -563,39 +563,3 @@ brw_get_fast_clear_rect(const struct isl_device *dev,
    *x1 = ALIGN(*x1, x_align) / x_scaledown;
    *y1 = ALIGN(*y1, y_align) / y_scaledown;
 }
-
-void
-brw_get_ccs_resolve_rect(const struct isl_device *dev,
-                         const struct isl_surf *ccs_surf,
-                         unsigned *x0, unsigned *y0,
-                         unsigned *x1, unsigned *y1)
-{
-   unsigned x_scaledown, y_scaledown;
-
-   /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
-    *
-    *     A rectangle primitive must be scaled down by the following factors
-    *     with respect to render target being resolved.
-    *
-    * The scaledown factors in the table that follows are related to the block
-    * size of the CCS format.  For IVB and HSW, we divide by two, for BDW we
-    * multiply by 8 and 16. On Sky Lake, we multiply by 8.
-    */
-   const struct isl_format_layout *fmtl =
-      isl_format_get_layout(ccs_surf->format);
-   assert(fmtl->txc == ISL_TXC_CCS);
-
-   if (ISL_DEV_GEN(dev) >= 9) {
-      x_scaledown = fmtl->bw * 8;
-      y_scaledown = fmtl->bh * 8;
-   } else if (ISL_DEV_GEN(dev) >= 8) {
-      x_scaledown = fmtl->bw * 8;
-      y_scaledown = fmtl->bh * 16;
-   } else {
-      x_scaledown = fmtl->bw / 2;
-      y_scaledown = fmtl->bh / 2;
-   }
-   *x0 = *y0 = 0;
-   *x1 = ALIGN(ccs_surf->logical_level0_px.width, x_scaledown) / x_scaledown;
-   *y1 = ALIGN(ccs_surf->logical_level0_px.height, y_scaledown) / y_scaledown;
-}
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.h b/src/mesa/drivers/dri/i965/brw_meta_util.h
index 79a777f..d517237 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.h
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.h
@@ -48,12 +48,6 @@ brw_get_fast_clear_rect(const struct isl_device *dev,
                         unsigned *x0, unsigned *y0,
                         unsigned *x1, unsigned *y1);
 
-void
-brw_get_ccs_resolve_rect(const struct isl_device *dev,
-                         const struct isl_surf *ccs_surf,
-                         unsigned *x0, unsigned *y0,
-                         unsigned *x1, unsigned *y1);
-
 bool
 brw_meta_set_fast_clear_color(struct brw_context *brw,
                               struct intel_mipmap_tree *mt,
-- 
2.5.0.400.gff86faf