[Mesa-dev] [PATCH v3] i965/vec4: make offset() operate in terms of channels instead of full registers

[Iago Toral Quiroga]

This will make it more consistent with the FS implementation of the same
helper and will provide more flexibility that will come in handy, for
example, when we add a SIMD lowering pass in the vec4 backend.

v2:
 - Move the switch statement to an add_byte_offset helper that takes a pointer
   to a backend_red so we can reuse the byte offset logic for src_reg and
   dst_reg (Iago)
 - Remove the assert on the register file, it is redundant with the switch
   (Michael Schellenberger)
 - Fix use of '=' instead of '==' (Michael Schellenberger,
   Francesco Ansanelli)

v3:
 - Add a byte_offset() helper too for consistency with the FS backend
   (Michael Schellenberger)
---
 src/mesa/drivers/dri/i965/brw_ir_vec4.h | 48 +++++++++++++++++++++++++++------
 1 file changed, 40 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 81b6a13..0dec00d 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -60,15 +60,42 @@ retype(src_reg reg, enum brw_reg_type type)
    return reg;
 }
 
+static inline void
+add_byte_offset(backend_reg *reg, unsigned delta)
+{
+   switch (reg->file) {
+   case BAD_FILE:
+      break;
+   case MRF:
+   case VGRF:
+   case ATTR:
+   case UNIFORM: {
+      const unsigned suboffset = reg->subreg_offset + delta;
+      reg->reg_offset += suboffset / REG_SIZE;
+      reg->subreg_offset += suboffset % REG_SIZE;
+      /* Align16 requires that register accesses are 16-byte aligned */
+      assert(reg->subreg_offset % 16 == 0);
+      break;
+   }
+   default:
+      assert(delta == 0);
+   }
+}
+
 static inline src_reg
-offset(src_reg reg, unsigned delta)
+byte_offset(src_reg reg, unsigned delta)
 {
-   assert(delta == 0 ||
-          (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
-   reg.reg_offset += delta;
+   add_byte_offset(&reg, delta);
    return reg;
 }
 
+static inline src_reg
+offset(src_reg reg, unsigned width, unsigned delta)
+{
+   unsigned bytes = delta * width * type_sz(reg.type);
+   return byte_offset(reg, bytes);
+}
+
 /**
  * Reswizzle a given source register.
  * \sa brw_swizzle().
@@ -130,15 +157,20 @@ retype(dst_reg reg, enum brw_reg_type type)
 }
 
 static inline dst_reg
-offset(dst_reg reg, unsigned delta)
+byte_offset(dst_reg reg, unsigned delta)
 {
-   assert(delta == 0 ||
-          (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
-   reg.reg_offset += delta;
+   add_byte_offset(&reg, delta);
    return reg;
 }
 
 static inline dst_reg
+offset(dst_reg reg, unsigned width, unsigned delta)
+{
+   unsigned bytes = delta * width * type_sz(reg.type);
+   return byte_offset(reg, bytes);
+}
+
+static inline dst_reg
 writemask(dst_reg reg, unsigned mask)
 {
    assert(reg.file != IMM);
-- 
2.7.4