[Mesa-dev] [PATCH 13/13] i965: use nir unrolling for scalar backend
Timothy Arceri
timothy.arceri at collabora.com
Mon Aug 29 04:59:21 UTC 2016
---
src/compiler/glsl/glsl_parser_extras.cpp | 12 +++++++-----
src/compiler/nir/nir_metadata.c | 2 ++
src/mesa/drivers/dri/i965/brw_compiler.c | 6 +++++-
src/mesa/drivers/dri/i965/brw_nir.c | 4 ++++
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp
index 80f37f3..43272fd 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -2053,12 +2053,14 @@ do_common_optimization(exec_list *ir, bool linked,
OPT(optimize_split_arrays, ir, linked);
OPT(optimize_redundant_jumps, ir);
- loop_state *ls = analyze_loop_variables(ir);
- if (ls->loop_found) {
- OPT(set_loop_controls, ir, ls);
- OPT(unroll_loops, ir, ls, options);
+ if (options->MaxUnrollIterations != 0) {
+ loop_state *ls = analyze_loop_variables(ir);
+ if (ls->loop_found) {
+ OPT(set_loop_controls, ir, ls);
+ OPT(unroll_loops, ir, ls, options);
+ }
+ delete ls;
}
- delete ls;
#undef OPT
diff --git a/src/compiler/nir/nir_metadata.c b/src/compiler/nir/nir_metadata.c
index 9e1cff5..b163377 100644
--- a/src/compiler/nir/nir_metadata.c
+++ b/src/compiler/nir/nir_metadata.c
@@ -41,6 +41,8 @@ nir_metadata_require(nir_function_impl *impl, nir_metadata required)
nir_calc_dominance_impl(impl);
if (NEEDS_UPDATE(nir_metadata_live_ssa_defs))
nir_live_ssa_defs_impl(impl);
+ if (NEEDS_UPDATE(nir_metadata_loop_analysis))
+ nir_loop_analyze_impl(impl);
#undef NEEDS_UPDATE
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c b/src/mesa/drivers/dri/i965/brw_compiler.c
index afb70a1..df570bf 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -55,6 +55,7 @@ static const struct nir_shader_compiler_options scalar_nir_options = {
.lower_unpack_snorm_4x8 = true,
.lower_unpack_unorm_2x16 = true,
.lower_unpack_unorm_4x8 = true,
+ .max_unroll_iterations = 32,
};
static const struct nir_shader_compiler_options vector_nir_options = {
@@ -75,6 +76,7 @@ static const struct nir_shader_compiler_options vector_nir_options = {
.lower_unpack_unorm_2x16 = true,
.lower_extract_byte = true,
.lower_extract_word = true,
+ .max_unroll_iterations = 0,
};
static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
@@ -92,6 +94,7 @@ static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
.lower_unpack_unorm_2x16 = true,
.lower_extract_byte = true,
.lower_extract_word = true,
+ .max_unroll_iterations = 0,
};
struct brw_compiler *
@@ -119,7 +122,6 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
- compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
compiler->glsl_compiler_options[i].MaxIfDepth =
devinfo->gen < 6 ? 16 : UINT_MAX;
@@ -140,8 +142,10 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
if (is_scalar) {
+ compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
} else {
+ compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
compiler->glsl_compiler_options[i].NirOptions =
devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
}
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index b8457d2..3cf1046 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -391,6 +391,10 @@ nir_optimize(nir_shader *nir, bool is_scalar)
OPT(nir_opt_algebraic);
OPT(nir_opt_constant_folding);
OPT(nir_opt_dead_cf);
+ if (nir->options->max_unroll_iterations != 0) {
+ OPT_V(nir_to_lcssa);
+ OPT(nir_opt_loop_unroll);
+ }
OPT(nir_opt_remove_phis);
OPT(nir_opt_undef);
OPT_V(nir_lower_doubles, nir_lower_drcp |
--
2.7.4
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