[Mesa-dev] [PATCH 19/20] gallium/radeon: set VPORT_ZMIN/MAX registers correctly
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Mon Aug 29 20:33:12 UTC 2016
On Mon, Aug 29, 2016 at 5:28 PM, Marek Olšák <maraeo at gmail.com> wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Calculate depth ranges from viewport states and
> pipe_rasterizer_state::clip_halfz.
>
> The evergreend.h change is required to silence a warning.
>
> This fixes this recently updated piglit: arb_depth_clamp/depth-clamp-range
> ---
> src/gallium/drivers/r600/evergreen_state.c | 1 +
> src/gallium/drivers/r600/evergreend.h | 4 +-
> src/gallium/drivers/r600/r600_hw_context.c | 1 +
> src/gallium/drivers/r600/r600_pipe.h | 1 +
> src/gallium/drivers/r600/r600_state.c | 1 +
> src/gallium/drivers/r600/r600_state_common.c | 2 +-
> src/gallium/drivers/radeon/r600_pipe_common.h | 5 +-
> src/gallium/drivers/radeon/r600_viewport.c | 73 ++++++++++++++++++++++++---
> src/gallium/drivers/radeon/r600d_common.h | 2 +
> src/gallium/drivers/radeonsi/si_hw_context.c | 1 +
> src/gallium/drivers/radeonsi/si_state.c | 3 +-
> src/gallium/drivers/radeonsi/si_state.h | 1 +
> 12 files changed, 82 insertions(+), 13 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
> index 11c8161..5ca5453 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -466,20 +466,21 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
> float psize_min, psize_max;
> struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
>
> if (!rs) {
> return NULL;
> }
>
> r600_init_command_buffer(&rs->buffer, 30);
>
> rs->scissor_enable = state->scissor;
> + rs->clip_halfz = state->clip_halfz;
> rs->flatshade = state->flatshade;
> rs->sprite_coord_enable = state->sprite_coord_enable;
> rs->two_side = state->light_twoside;
> rs->clip_plane_enable = state->clip_plane_enable;
> rs->pa_sc_line_stipple = state->line_stipple_enable ?
> S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
> S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
> rs->pa_cl_clip_cntl =
> S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
> S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
> diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
> index a81b6c5..3f33e42 100644
> --- a/src/gallium/drivers/r600/evergreend.h
> +++ b/src/gallium/drivers/r600/evergreend.h
> @@ -1856,22 +1856,22 @@
> #define R_0283DC_SQ_VTX_SEMANTIC_23 0x000283DC
> #define R_0283E0_SQ_VTX_SEMANTIC_24 0x000283E0
> #define R_0283E4_SQ_VTX_SEMANTIC_25 0x000283E4
> #define R_0283E8_SQ_VTX_SEMANTIC_26 0x000283E8
> #define R_0283EC_SQ_VTX_SEMANTIC_27 0x000283EC
> #define R_0283F0_SQ_VTX_SEMANTIC_28 0x000283F0
> #define R_0283F4_SQ_VTX_SEMANTIC_29 0x000283F4
> #define R_0283F8_SQ_VTX_SEMANTIC_30 0x000283F8
> #define R_0283FC_SQ_VTX_SEMANTIC_31 0x000283FC
> #define R_0288F0_SQ_VTX_SEMANTIC_CLEAR 0x000288F0
> -#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x000282D0
> -#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x000282D4
> +#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
> +#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
Could you align these the same as the other registers.
With that, patches 1-11,13-16,18-20 are
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Patches 12 and 17 look good to me, but I can't ascertain anything
about correctness as they almost entirely depend on unodcumented
hardware facts that I don't know and hence don't get my r-b. I don't
if there is a preferred tag for this?
Yours sincerely,
Bas Nieuwenhuizen
> #define R_028400_VGT_MAX_VTX_INDX 0x00028400
> #define R_028404_VGT_MIN_VTX_INDX 0x00028404
> #define R_028408_VGT_INDX_OFFSET 0x00028408
> #define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x0002840C
> #define R_028414_CB_BLEND_RED 0x00028414
> #define R_028418_CB_BLEND_GREEN 0x00028418
> #define R_02841C_CB_BLEND_BLUE 0x0002841C
> #define R_028420_CB_BLEND_ALPHA 0x00028420
> #define R_028438_SX_ALPHA_REF 0x00028438
> #define R_02843C_PA_CL_VPORT_XSCALE_0 0x0002843C
> diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
> index 58ba09d..dc5ad75 100644
> --- a/src/gallium/drivers/r600/r600_hw_context.c
> +++ b/src/gallium/drivers/r600/r600_hw_context.c
> @@ -305,20 +305,21 @@ void r600_begin_new_cs(struct r600_context *ctx)
> r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
> r600_mark_atom_dirty(ctx, &ctx->db_state.atom);
> r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
> r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_PS].atom);
> r600_mark_atom_dirty(ctx, &ctx->poly_offset_state.atom);
> r600_mark_atom_dirty(ctx, &ctx->vgt_state.atom);
> r600_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
> ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> r600_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
> ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> + ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> r600_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
> if (ctx->b.chip_class <= EVERGREEN) {
> r600_mark_atom_dirty(ctx, &ctx->config_state.atom);
> }
> r600_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
> r600_mark_atom_dirty(ctx, &ctx->vertex_fetch_shader.atom);
> r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_ES].atom);
> r600_mark_atom_dirty(ctx, &ctx->shader_stages.atom);
> if (ctx->gs_shader) {
> r600_mark_atom_dirty(ctx, &ctx->hw_shader_stages[R600_HW_STAGE_GS].atom);
> diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
> index e1b2aed..4403aca 100644
> --- a/src/gallium/drivers/r600/r600_pipe.h
> +++ b/src/gallium/drivers/r600/r600_pipe.h
> @@ -269,20 +269,21 @@ struct r600_rasterizer_state {
> unsigned clip_plane_enable;
> unsigned pa_sc_line_stipple;
> unsigned pa_cl_clip_cntl;
> unsigned pa_su_sc_mode_cntl;
> float offset_units;
> float offset_scale;
> bool offset_enable;
> bool offset_units_unscaled;
> bool scissor_enable;
> bool multisample_enable;
> + bool clip_halfz;
> };
>
> struct r600_poly_offset_state {
> struct r600_atom atom;
> enum pipe_format zs_format;
> float offset_units;
> float offset_scale;
> bool offset_units_unscaled;
> };
>
> diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
> index fb2861a..c8768e0 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -465,20 +465,21 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
> float psize_min, psize_max;
> struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
>
> if (!rs) {
> return NULL;
> }
>
> r600_init_command_buffer(&rs->buffer, 30);
>
> rs->scissor_enable = state->scissor;
> + rs->clip_halfz = state->clip_halfz;
> rs->flatshade = state->flatshade;
> rs->sprite_coord_enable = state->sprite_coord_enable;
> rs->two_side = state->light_twoside;
> rs->clip_plane_enable = state->clip_plane_enable;
> rs->pa_sc_line_stipple = state->line_stipple_enable ?
> S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
> S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
> rs->pa_cl_clip_cntl =
> S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
> S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
> diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
> index 0349432..32eab83 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -359,21 +359,21 @@ static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
> }
>
> /* Update clip_misc_state. */
> if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
> rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
> rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
> rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
> r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
> }
>
> - r600_set_scissor_enable(&rctx->b, rs->scissor_enable);
> + r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
>
> /* Re-emit PA_SC_LINE_STIPPLE. */
> rctx->last_primitive_type = -1;
> }
>
> static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
> {
> struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
>
> r600_release_command_buffer(&rs->buffer);
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
> index d821eaa..aa40a54 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -479,20 +479,21 @@ struct r600_signed_scissor {
>
> struct r600_scissors {
> struct r600_atom atom;
> unsigned dirty_mask;
> struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
> };
>
> struct r600_viewports {
> struct r600_atom atom;
> unsigned dirty_mask;
> + unsigned depth_range_dirty_mask;
> struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
> struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
> };
>
> struct r600_ring {
> struct radeon_winsys_cs *cs;
> void (*flush)(void *ctx, unsigned flags,
> struct pipe_fence_handle **fence);
> };
>
> @@ -530,20 +531,21 @@ struct r600_common_context {
>
> /* Current unaccounted memory usage. */
> uint64_t vram;
> uint64_t gtt;
>
> /* States. */
> struct r600_streamout streamout;
> struct r600_scissors scissors;
> struct r600_viewports viewports;
> bool scissor_enabled;
> + bool clip_halfz;
> bool vs_writes_viewport_index;
> bool vs_disables_clipping_viewport;
>
> /* Additional context states. */
> unsigned flags; /* flush flags */
>
> /* Queries. */
> /* Maintain the list of active queries for pausing between IBs. */
> int num_occlusion_queries;
> int num_perfect_occlusion_queries;
> @@ -786,21 +788,22 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
> unsigned *buffers, unsigned *dirty_cbufs,
> const union pipe_color_union *color);
> bool r600_texture_disable_dcc(struct r600_common_context *rctx,
> struct r600_texture *rtex);
> void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
> void r600_init_context_texture_functions(struct r600_common_context *rctx);
>
> /* r600_viewport.c */
> void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
> struct pipe_scissor_state *scissor);
> -void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
> +void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
> + bool scissor_enable, bool clip_halfz);
> void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
> struct tgsi_shader_info *info);
> void r600_init_viewport_functions(struct r600_common_context *rctx);
>
> /* cayman_msaa.c */
> extern const uint32_t eg_sample_locs_2x[4];
> extern const unsigned eg_max_dist_2x;
> extern const uint32_t eg_sample_locs_4x[4];
> extern const unsigned eg_max_dist_4x;
> void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
> diff --git a/src/gallium/drivers/radeon/r600_viewport.c b/src/gallium/drivers/radeon/r600_viewport.c
> index 2d68783..2de1382 100644
> --- a/src/gallium/drivers/radeon/r600_viewport.c
> +++ b/src/gallium/drivers/radeon/r600_viewport.c
> @@ -15,20 +15,21 @@
> * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
> * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> * USE OR OTHER DEALINGS IN THE SOFTWARE.
> */
>
> #include "r600_cs.h"
> +#include "util/u_viewport.h"
> #include "tgsi/tgsi_scan.h"
>
> #define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
>
> static void r600_set_scissor_states(struct pipe_context *ctx,
> unsigned start_slot,
> unsigned num_scissors,
> const struct pipe_scissor_state *state)
> {
> struct r600_common_context *rctx = (struct r600_common_context *)ctx;
> @@ -253,50 +254,53 @@ static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_ato
> r600_emit_guardband(rctx, &max_vp_scissor);
> rctx->scissors.dirty_mask = 0;
> }
>
> static void r600_set_viewport_states(struct pipe_context *ctx,
> unsigned start_slot,
> unsigned num_viewports,
> const struct pipe_viewport_state *state)
> {
> struct r600_common_context *rctx = (struct r600_common_context *)ctx;
> + unsigned mask;
> int i;
>
> for (i = 0; i < num_viewports; i++) {
> unsigned index = start_slot + i;
>
> rctx->viewports.states[index] = state[i];
> r600_get_scissor_from_viewport(rctx, &state[i],
> &rctx->viewports.as_scissor[index]);
> }
>
> - rctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
> - rctx->scissors.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
> + mask = ((1 << num_viewports) - 1) << start_slot;
> + rctx->viewports.dirty_mask |= mask;
> + rctx->viewports.depth_range_dirty_mask |= mask;
> + rctx->scissors.dirty_mask |= mask;
> rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
> rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
> }
>
> static void r600_emit_one_viewport(struct r600_common_context *rctx,
> struct pipe_viewport_state *state)
> {
> struct radeon_winsys_cs *cs = rctx->gfx.cs;
>
> radeon_emit(cs, fui(state->scale[0]));
> radeon_emit(cs, fui(state->translate[0]));
> radeon_emit(cs, fui(state->scale[1]));
> radeon_emit(cs, fui(state->translate[1]));
> radeon_emit(cs, fui(state->scale[2]));
> radeon_emit(cs, fui(state->translate[2]));
> }
>
> -static void r600_emit_viewports(struct r600_common_context *rctx, struct r600_atom *atom)
> +static void r600_emit_viewports(struct r600_common_context *rctx)
> {
> struct radeon_winsys_cs *cs = rctx->gfx.cs;
> struct pipe_viewport_state *states = rctx->viewports.states;
> unsigned mask = rctx->viewports.dirty_mask;
>
> /* The simple case: Only 1 viewport is active. */
> if (!rctx->vs_writes_viewport_index) {
> if (!(mask & 1))
> return;
>
> @@ -312,27 +316,78 @@ static void r600_emit_viewports(struct r600_common_context *rctx, struct r600_at
> u_bit_scan_consecutive_range(&mask, &start, &count);
>
> radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
> start * 4 * 6, count * 6);
> for (i = start; i < start+count; i++)
> r600_emit_one_viewport(rctx, &states[i]);
> }
> rctx->viewports.dirty_mask = 0;
> }
>
> -void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable)
> +static void r600_emit_depth_ranges(struct r600_common_context *rctx)
> {
> - if (rctx->scissor_enabled != enable) {
> - rctx->scissor_enabled = enable;
> + struct radeon_winsys_cs *cs = rctx->gfx.cs;
> + struct pipe_viewport_state *states = rctx->viewports.states;
> + unsigned mask = rctx->viewports.depth_range_dirty_mask;
> + float zmin, zmax;
> +
> + /* The simple case: Only 1 viewport is active. */
> + if (!rctx->vs_writes_viewport_index) {
> + if (!(mask & 1))
> + return;
> +
> + util_viewport_zmin_zmax(&states[0], rctx->clip_halfz, &zmin, &zmax);
> +
> + radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
> + radeon_emit(cs, fui(zmin));
> + radeon_emit(cs, fui(zmax));
> + rctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
> + return;
> + }
> +
> + while (mask) {
> + int start, count, i;
> +
> + u_bit_scan_consecutive_range(&mask, &start, &count);
> +
> + radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
> + start * 4 * 2, count * 2);
> + for (i = start; i < start+count; i++) {
> + util_viewport_zmin_zmax(&states[i], rctx->clip_halfz, &zmin, &zmax);
> + radeon_emit(cs, fui(zmin));
> + radeon_emit(cs, fui(zmax));
> + }
> + }
> + rctx->viewports.depth_range_dirty_mask = 0;
> +}
> +
> +static void r600_emit_viewport_states(struct r600_common_context *rctx,
> + struct r600_atom *atom)
> +{
> + r600_emit_viewports(rctx);
> + r600_emit_depth_ranges(rctx);
> +}
> +
> +/* Set viewport dependencies on pipe_rasterizer_state. */
> +void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
> + bool scissor_enable, bool clip_halfz)
> +{
> + if (rctx->scissor_enabled != scissor_enable) {
> + rctx->scissor_enabled = scissor_enable;
> rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
> }
> + if (rctx->clip_halfz != clip_halfz) {
> + rctx->clip_halfz = clip_halfz;
> + rctx->viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> + rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
> + }
> }
>
> /**
> * Normally, we only emit 1 viewport and 1 scissor if no shader is using
> * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
> * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
> * called to emit the rest.
> */
> void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
> struct tgsi_shader_info *info)
> @@ -352,25 +407,27 @@ void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
> rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
> }
>
> /* Viewport index handling. */
> rctx->vs_writes_viewport_index = info->writes_viewport_index;
> if (!rctx->vs_writes_viewport_index)
> return;
>
> if (rctx->scissors.dirty_mask)
> rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
> - if (rctx->viewports.dirty_mask)
> +
> + if (rctx->viewports.dirty_mask ||
> + rctx->viewports.depth_range_dirty_mask)
> rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
> }
>
> void r600_init_viewport_functions(struct r600_common_context *rctx)
> {
> rctx->scissors.atom.emit = r600_emit_scissors;
> - rctx->viewports.atom.emit = r600_emit_viewports;
> + rctx->viewports.atom.emit = r600_emit_viewport_states;
>
> rctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
> rctx->viewports.atom.num_dw = 2 + 16 * 6;
>
> rctx->b.set_scissor_states = r600_set_scissor_states;
> rctx->b.set_viewport_states = r600_set_viewport_states;
> }
> diff --git a/src/gallium/drivers/radeon/r600d_common.h b/src/gallium/drivers/radeon/r600d_common.h
> index 6f534b3..3dbe43a 100644
> --- a/src/gallium/drivers/radeon/r600d_common.h
> +++ b/src/gallium/drivers/radeon/r600d_common.h
> @@ -239,12 +239,14 @@
> #define C_028250_TL_Y 0x8000FFFF
> #define S_028250_WINDOW_OFFSET_DISABLE(x) (((unsigned)(x) & 0x1) << 31)
> #define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
> #define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
> #define S_028254_BR_X(x) (((unsigned)(x) & 0x7FFF) << 0)
> #define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF)
> #define C_028254_BR_X 0xFFFF8000
> #define S_028254_BR_Y(x) (((unsigned)(x) & 0x7FFF) << 16)
> #define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF)
> #define C_028254_BR_Y 0x8000FFFF
> +#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
> +#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
>
> #endif
> diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
> index aeccb2d..a03b327 100644
> --- a/src/gallium/drivers/radeonsi/si_hw_context.c
> +++ b/src/gallium/drivers/radeonsi/si_hw_context.c
> @@ -206,20 +206,21 @@ void si_begin_new_cs(struct si_context *ctx)
> si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
> si_mark_atom_dirty(ctx, &ctx->db_render_state);
> si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
> si_mark_atom_dirty(ctx, &ctx->spi_map);
> si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
> si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
> si_all_descriptors_begin_new_cs(ctx);
>
> ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> + ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
> si_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
> si_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
>
> r600_postflush_resume_features(&ctx->b);
>
> assert(!ctx->b.gfx.cs->prev_dw);
> ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
>
> /* Invalidate various draw states so that they are emitted before
> * the first draw call. */
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 803a021..526f628 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -725,20 +725,21 @@ static void *si_create_rs_state(struct pipe_context *ctx,
> struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
> struct si_pm4_state *pm4 = &rs->pm4;
> unsigned tmp, i;
> float psize_min, psize_max;
>
> if (!rs) {
> return NULL;
> }
>
> rs->scissor_enable = state->scissor;
> + rs->clip_halfz = state->clip_halfz;
> rs->two_side = state->light_twoside;
> rs->multisample_enable = state->multisample;
> rs->force_persample_interp = state->force_persample_interp;
> rs->clip_plane_enable = state->clip_plane_enable;
> rs->line_stipple_enable = state->line_stipple_enable;
> rs->poly_stipple_enable = state->poly_stipple_enable;
> rs->line_smooth = state->line_smooth;
> rs->poly_smooth = state->poly_smooth;
> rs->uses_poly_offset = state->offset_point || state->offset_line ||
> state->offset_tri;
> @@ -864,21 +865,21 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
> return;
>
> if (sctx->framebuffer.nr_samples > 1 &&
> (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
> si_mark_atom_dirty(sctx, &sctx->db_render_state);
>
> if (sctx->b.family >= CHIP_POLARIS10)
> si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
> }
>
> - r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
> + r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
>
> si_pm4_bind_state(sctx, rasterizer, rs);
> si_update_poly_offset_state(sctx);
>
> si_mark_atom_dirty(sctx, &sctx->clip_regs);
> sctx->do_update_shaders = true;
> }
>
> static void si_delete_rs_state(struct pipe_context *ctx, void *state)
> {
> diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
> index f4f7575..d0e519c 100644
> --- a/src/gallium/drivers/radeonsi/si_state.h
> +++ b/src/gallium/drivers/radeonsi/si_state.h
> @@ -69,20 +69,21 @@ struct si_state_rasterizer {
> unsigned pa_sc_line_stipple;
> unsigned pa_cl_clip_cntl;
> unsigned clip_plane_enable;
> bool poly_stipple_enable;
> bool line_smooth;
> bool poly_smooth;
> bool uses_poly_offset;
> bool clamp_fragment_color;
> bool rasterizer_discard;
> bool scissor_enable;
> + bool clip_halfz;
> };
>
> struct si_dsa_stencil_ref_part {
> uint8_t valuemask[2];
> uint8_t writemask[2];
> };
>
> struct si_state_dsa {
> struct si_pm4_state pm4;
> unsigned alpha_func;
> --
> 2.7.4
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
More information about the mesa-dev
mailing list