[Mesa-dev] [PATCH 16/20] radeonsi: fix variable naming in si_emit_cache_flush
Edward O'Callaghan
funfunctor at folklore1984.net
Tue Aug 30 09:15:05 UTC 2016
Reviewed-by: Edward O'Callaghan <funfunctor at folklore1984.net>
On 08/30/2016 01:28 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
> src/gallium/drivers/radeonsi/si_state_draw.c | 62 ++++++++++++++--------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index ddcb904..0a91291 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -689,158 +689,158 @@ static void si_emit_draw_packets(struct si_context *sctx,
> radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
> } else {
> radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
> radeon_emit(cs, info->count);
> radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
> S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
> }
> }
> }
>
> -void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
> +void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom)
> {
> - struct r600_common_context *sctx = &si_ctx->b;
> - struct radeon_winsys_cs *cs = sctx->gfx.cs;
> + struct r600_common_context *rctx = &sctx->b;
> + struct radeon_winsys_cs *cs = rctx->gfx.cs;
> uint32_t cp_coher_cntl = 0;
>
> /* SI has a bug that it always flushes ICACHE and KCACHE if either
> * bit is set. An alternative way is to write SQC_CACHES, but that
> * doesn't seem to work reliably. Since the bug doesn't affect
> * correctness (it only does more work than necessary) and
> * the performance impact is likely negligible, there is no plan
> * to add a workaround for it.
> */
>
> - if (sctx->flags & SI_CONTEXT_INV_ICACHE)
> + if (rctx->flags & SI_CONTEXT_INV_ICACHE)
> cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
> - if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
> + if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
> cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
>
> - if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
> + if (rctx->flags & SI_CONTEXT_INV_VMEM_L1)
> cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
> - if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
> + if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
> cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
>
> - if (sctx->chip_class >= VI)
> + if (rctx->chip_class >= VI)
> cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
> }
>
> - if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
> + if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
> cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
> S_0085F0_CB0_DEST_BASE_ENA(1) |
> S_0085F0_CB1_DEST_BASE_ENA(1) |
> S_0085F0_CB2_DEST_BASE_ENA(1) |
> S_0085F0_CB3_DEST_BASE_ENA(1) |
> S_0085F0_CB4_DEST_BASE_ENA(1) |
> S_0085F0_CB5_DEST_BASE_ENA(1) |
> S_0085F0_CB6_DEST_BASE_ENA(1) |
> S_0085F0_CB7_DEST_BASE_ENA(1);
>
> /* Necessary for DCC */
> - if (sctx->chip_class >= VI) {
> + if (rctx->chip_class >= VI) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
> EVENT_INDEX(5));
> radeon_emit(cs, 0);
> radeon_emit(cs, 0);
> radeon_emit(cs, 0);
> radeon_emit(cs, 0);
> }
> }
> - if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
> + if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
> cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
> S_0085F0_DB_DEST_BASE_ENA(1);
> }
>
> - if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
> + if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
> /* needed for wait for idle in SURFACE_SYNC */
> - assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
> + assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
> }
> - if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
> + if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
> /* needed for wait for idle in SURFACE_SYNC */
> - assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
> + assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
> }
>
> /* Wait for shader engines to go idle.
> * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
> * for everything including CB/DB cache flushes.
> */
> - if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
> + if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
> SI_CONTEXT_FLUSH_AND_INV_DB))) {
> - if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
> + if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
> /* Only count explicit shader flushes, not implicit ones
> * done by SURFACE_SYNC.
> */
> - sctx->num_vs_flushes++;
> - sctx->num_ps_flushes++;
> - } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
> + rctx->num_vs_flushes++;
> + rctx->num_ps_flushes++;
> + } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
> - sctx->num_vs_flushes++;
> + rctx->num_vs_flushes++;
> }
> }
>
> - if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
> - si_ctx->compute_is_busy) {
> + if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
> + sctx->compute_is_busy) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
> - sctx->num_cs_flushes++;
> - si_ctx->compute_is_busy = false;
> + rctx->num_cs_flushes++;
> + sctx->compute_is_busy = false;
> }
>
> /* VGT state synchronization. */
> - if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
> + if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
> }
> - if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
> + if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
> }
>
> /* Make sure ME is idle (it executes most packets) before continuing.
> * This prevents read-after-write hazards between PFP and ME.
> */
> - if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
> + if (cp_coher_cntl || (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
> radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
> radeon_emit(cs, 0);
> }
>
> /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
> * Therefore, it should be last. Done in PFP.
> */
> if (cp_coher_cntl) {
> /* ACQUIRE_MEM is only required on a compute ring. */
> radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
> radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
> radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
> radeon_emit(cs, 0); /* CP_COHER_BASE */
> radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
> }
>
> - if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
> + if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
> EVENT_INDEX(0));
> - } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
> + } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
> EVENT_INDEX(0));
> }
>
> - sctx->flags = 0;
> + rctx->flags = 0;
> }
>
> static void si_get_draw_start_count(struct si_context *sctx,
> const struct pipe_draw_info *info,
> unsigned *start, unsigned *count)
> {
> if (info->indirect) {
> struct r600_resource *indirect =
> (struct r600_resource*)info->indirect;
> int *data = r600_buffer_map_sync_with_rings(&sctx->b,
>
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