[Mesa-dev] i965: Hardware assisted layered clears

[Topi Pohjolainen]

This series requests hardware to generate as many copies of drawing
primitives as there are layers to be cleared instead of submitting
separate render passes for the layers.

In case of patches 2, 3, 8 and 9 I'm open to suggestions. There
probably are other (better?) alternatives.

CC: Jason Ekstrand <jason.ekstrand at intel.com>

Topi Pohjolainen (12):
  i965/rbc: Allow integer formats as advertised in isl_format.c
  i965/rbc: Set aux surface unconditionally for sampling engine
  isl/gen8+: Allow 3D auxiliary surfaces
  i965/rbc: Allocate mcs directly
  i965/blorp: Skip redundant re-fast clear for non-compressed
  i965/meta: Split conversion of color and setting it
  i965/blorp: Instruct vertex fetcher to provide prim instance id
  intel/blorp: Allow multiple layers
  intel/blorp: Allow single slice converter to suppress number of layers
  intel/blorp: Add plumbing for setting color clear layer count
  i965/blorp: Sanity check all layers before actual clear
  i965/blorp: Use hw generetad primitive copies for layered clears

 src/intel/blorp/blorp.c                          |  9 ++-
 src/intel/blorp/blorp.h                          |  6 +-
 src/intel/blorp/blorp_blit.c                     |  3 -
 src/intel/blorp/blorp_clear.c                    | 16 +++--
 src/intel/blorp/blorp_genX_exec.h                | 26 +++++--
 src/intel/isl/isl.c                              |  7 +-
 src/mesa/drivers/dri/i965/brw_blorp.c            | 87 ++++++++++++++----------
 src/mesa/drivers/dri/i965/brw_draw.c             |  4 +-
 src/mesa/drivers/dri/i965/brw_meta_util.c        | 56 ++++++++-------
 src/mesa/drivers/dri/i965/brw_meta_util.h        | 10 ++-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 46 ++++++++++++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c    | 68 +++++-------------
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h    |  7 +-
 13 files changed, 199 insertions(+), 146 deletions(-)

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2.5.5