[Mesa-dev] [PATCH 5/8] anv: Leverage the shared L3$ config code
Jason Ekstrand
jason at jlekstrand.net
Wed Aug 31 20:56:55 UTC 2016
When Jordan first implement L3$ configuration for Vulkan, he copied+pasted
from the GL driver because we had no good place to share it. Now that we
have src/intel/common, we should be sharing these tables.
Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
---
src/intel/vulkan/anv_private.h | 6 +-
src/intel/vulkan/genX_l3.c | 376 ++++-------------------------------------
2 files changed, 37 insertions(+), 345 deletions(-)
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 7cab99e..5486d92 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -52,7 +52,7 @@ typedef struct xcb_connection_t xcb_connection_t;
typedef uint32_t xcb_visualid_t;
typedef uint32_t xcb_window_t;
-struct anv_l3_config;
+struct gen_l3_config;
#include <vulkan/vulkan.h>
#include <vulkan/vulkan_intel.h>
@@ -1224,7 +1224,7 @@ struct anv_attachment_state {
struct anv_cmd_state {
/* PIPELINE_SELECT.PipelineSelection */
uint32_t current_pipeline;
- const struct anv_l3_config * current_l3_config;
+ const struct gen_l3_config * current_l3_config;
uint32_t vb_dirty;
anv_cmd_dirty_mask_t dirty;
anv_cmd_dirty_mask_t compute_dirty;
@@ -1524,7 +1524,7 @@ struct anv_pipeline {
uint32_t start[MESA_SHADER_GEOMETRY + 1];
uint32_t size[MESA_SHADER_GEOMETRY + 1];
uint32_t entries[MESA_SHADER_GEOMETRY + 1];
- const struct anv_l3_config * l3_config;
+ const struct gen_l3_config * l3_config;
uint32_t total_size;
} urb;
diff --git a/src/intel/vulkan/genX_l3.c b/src/intel/vulkan/genX_l3.c
index 36bf57c..9efaeb1 100644
--- a/src/intel/vulkan/genX_l3.c
+++ b/src/intel/vulkan/genX_l3.c
@@ -23,293 +23,18 @@
#include "anv_private.h"
+#include "common/gen_l3_config.h"
#include "genxml/gen_macros.h"
#include "genxml/genX_pack.h"
/**
- * Chunk of L3 cache reserved for some specific purpose.
- */
-enum anv_l3_partition {
- /** Shared local memory. */
- L3P_SLM = 0,
- /** Unified return buffer. */
- L3P_URB,
- /** Union of DC and RO. */
- L3P_ALL,
- /** Data cluster RW partition. */
- L3P_DC,
- /** Union of IS, C and T. */
- L3P_RO,
- /** Instruction and state cache. */
- L3P_IS,
- /** Constant cache. */
- L3P_C,
- /** Texture cache. */
- L3P_T,
- /** Number of supported L3 partitions. */
- NUM_L3P
-};
-
-/**
- * L3 configuration represented as the number of ways allocated for each
- * partition. \sa get_l3_way_size().
- */
-struct anv_l3_config {
- unsigned n[NUM_L3P];
-};
-
-#if GEN_GEN == 7
-
-/**
- * IVB/HSW validated L3 configurations. The first entry will be used as
- * default by gen7_restore_default_l3_config(), otherwise the ordering is
- * unimportant.
- */
-static const struct anv_l3_config ivb_l3_configs[] = {
- /* SLM URB ALL DC RO IS C T */
- {{ 0, 32, 0, 0, 32, 0, 0, 0 }},
- {{ 0, 32, 0, 16, 16, 0, 0, 0 }},
- {{ 0, 32, 0, 4, 0, 8, 4, 16 }},
- {{ 0, 28, 0, 8, 0, 8, 4, 16 }},
- {{ 0, 28, 0, 16, 0, 8, 4, 8 }},
- {{ 0, 28, 0, 8, 0, 16, 4, 8 }},
- {{ 0, 28, 0, 0, 0, 16, 4, 16 }},
- {{ 0, 32, 0, 0, 0, 16, 0, 16 }},
- {{ 0, 28, 0, 4, 32, 0, 0, 0 }},
- {{ 16, 16, 0, 16, 16, 0, 0, 0 }},
- {{ 16, 16, 0, 8, 0, 8, 8, 8 }},
- {{ 16, 16, 0, 4, 0, 8, 4, 16 }},
- {{ 16, 16, 0, 4, 0, 16, 4, 8 }},
- {{ 16, 16, 0, 0, 32, 0, 0, 0 }},
- {{ 0 }}
-};
-
-#endif
-
-#if GEN_GEN == 7 && !GEN_IS_HASWELL
-
-/**
- * VLV validated L3 configurations. \sa ivb_l3_configs.
- */
-static const struct anv_l3_config vlv_l3_configs[] = {
- /* SLM URB ALL DC RO IS C T */
- {{ 0, 64, 0, 0, 32, 0, 0, 0 }},
- {{ 0, 80, 0, 0, 16, 0, 0, 0 }},
- {{ 0, 80, 0, 8, 8, 0, 0, 0 }},
- {{ 0, 64, 0, 16, 16, 0, 0, 0 }},
- {{ 0, 60, 0, 4, 32, 0, 0, 0 }},
- {{ 32, 32, 0, 16, 16, 0, 0, 0 }},
- {{ 32, 40, 0, 8, 16, 0, 0, 0 }},
- {{ 32, 40, 0, 16, 8, 0, 0, 0 }},
- {{ 0 }}
-};
-
-#endif
-
-#if GEN_GEN == 8
-
-/**
- * BDW validated L3 configurations. \sa ivb_l3_configs.
- */
-static const struct anv_l3_config bdw_l3_configs[] = {
- /* SLM URB ALL DC RO IS C T */
- {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
- {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
- {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
- {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
- {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
- {{ 24, 16, 48, 0, 0, 0, 0, 0 }},
- {{ 24, 16, 0, 16, 32, 0, 0, 0 }},
- {{ 24, 16, 0, 32, 16, 0, 0, 0 }},
- {{ 0 }}
-};
-
-#endif
-
-#if GEN_GEN == 8 || GEN_GEN == 9
-
-/**
- * CHV/SKL validated L3 configurations. \sa ivb_l3_configs.
- */
-static const struct anv_l3_config chv_l3_configs[] = {
- /* SLM URB ALL DC RO IS C T */
- {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
- {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
- {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
- {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
- {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
- {{ 32, 16, 48, 0, 0, 0, 0, 0 }},
- {{ 32, 16, 0, 16, 32, 0, 0, 0 }},
- {{ 32, 16, 0, 32, 16, 0, 0, 0 }},
- {{ 0 }}
-};
-
-#endif
-
-/**
- * Return a zero-terminated array of validated L3 configurations for the
- * specified device.
- */
-static inline const struct anv_l3_config *
-get_l3_configs(const struct gen_device_info *devinfo)
-{
- assert(devinfo->gen == GEN_GEN);
-#if GEN_IS_HASWELL
- return ivb_l3_configs;
-#elif GEN_GEN == 7
- return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
-#elif GEN_GEN == 8
- return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
-#elif GEN_GEN == 9
- return chv_l3_configs;
-#else
-#error GEN not supported
-#endif
-}
-
-/**
- * Return the size of an L3 way in KB.
- */
-static unsigned
-get_l3_way_size(const struct gen_device_info *devinfo)
-{
- if (devinfo->is_baytrail)
- return 2;
-
- else if (devinfo->is_cherryview || devinfo->gt == 1)
- return 4;
-
- else
- return 8 * devinfo->num_slices;
-}
-
-/**
- * L3 configuration represented as a vector of weights giving the desired
- * relative size of each partition. The scale is arbitrary, only the ratios
- * between weights will have an influence on the selection of the closest L3
- * configuration.
- */
-struct anv_l3_weights {
- float w[NUM_L3P];
-};
-
-/**
- * L1-normalize a vector of L3 partition weights.
- */
-static struct anv_l3_weights
-norm_l3_weights(struct anv_l3_weights w)
-{
- float sz = 0;
-
- for (unsigned i = 0; i < NUM_L3P; i++)
- sz += w.w[i];
-
- for (unsigned i = 0; i < NUM_L3P; i++)
- w.w[i] /= sz;
-
- return w;
-}
-
-/**
- * Get the relative partition weights of the specified L3 configuration.
- */
-static struct anv_l3_weights
-get_config_l3_weights(const struct anv_l3_config *cfg)
-{
- if (cfg) {
- struct anv_l3_weights w;
-
- for (unsigned i = 0; i < NUM_L3P; i++)
- w.w[i] = cfg->n[i];
-
- return norm_l3_weights(w);
- } else {
- const struct anv_l3_weights w = { { 0 } };
- return w;
- }
-}
-
-/**
- * Distance between two L3 configurations represented as vectors of weights.
- * Usually just the L1 metric except when the two configurations are
- * considered incompatible in which case the distance will be infinite. Note
- * that the compatibility condition is asymmetric -- They will be considered
- * incompatible whenever the reference configuration \p w0 requires SLM, DC,
- * or URB but \p w1 doesn't provide it.
- */
-static float
-diff_l3_weights(struct anv_l3_weights w0, struct anv_l3_weights w1)
-{
- if ((w0.w[L3P_SLM] && !w1.w[L3P_SLM]) ||
- (w0.w[L3P_DC] && !w1.w[L3P_DC] && !w1.w[L3P_ALL]) ||
- (w0.w[L3P_URB] && !w1.w[L3P_URB])) {
- return HUGE_VALF;
-
- } else {
- float dw = 0;
-
- for (unsigned i = 0; i < NUM_L3P; i++)
- dw += fabs(w0.w[i] - w1.w[i]);
-
- return dw;
- }
-}
-
-/**
- * Return the closest validated L3 configuration for the specified device and
- * weight vector.
- */
-static const struct anv_l3_config *
-get_l3_config(const struct gen_device_info *devinfo, struct anv_l3_weights w0)
-{
- const struct anv_l3_config *const cfgs = get_l3_configs(devinfo);
- const struct anv_l3_config *cfg_best = NULL;
- float dw_best = HUGE_VALF;
-
- for (const struct anv_l3_config *cfg = cfgs; cfg->n[L3P_URB]; cfg++) {
- const float dw = diff_l3_weights(w0, get_config_l3_weights(cfg));
-
- if (dw < dw_best) {
- cfg_best = cfg;
- dw_best = dw;
- }
- }
-
- return cfg_best;
-}
-
-/**
- * Return a reasonable default L3 configuration for the specified device based
- * on whether SLM and DC are required. In the non-SLM non-DC case the result
- * is intended to approximately resemble the hardware defaults.
- */
-static struct anv_l3_weights
-get_default_l3_weights(const struct gen_device_info *devinfo,
- bool needs_dc, bool needs_slm)
-{
- struct anv_l3_weights w = {{ 0 }};
-
- w.w[L3P_SLM] = needs_slm;
- w.w[L3P_URB] = 1.0;
-
- if (devinfo->gen >= 8) {
- w.w[L3P_ALL] = 1.0;
- } else {
- w.w[L3P_DC] = needs_dc ? 0.1 : 0;
- w.w[L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
- }
-
- return norm_l3_weights(w);
-}
-
-/**
* Calculate the desired L3 partitioning based on the current state of the
* pipeline. For now this simply returns the conservative defaults calculated
* by get_default_l3_weights(), but we could probably do better by gathering
* more statistics from the pipeline state (e.g. guess of expected URB usage
* and bound surfaces), or by using feed-back from performance counters.
*/
-static struct anv_l3_weights
+static struct gen_l3_weights
get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
{
bool needs_dc = false, needs_slm = false;
@@ -325,8 +50,8 @@ get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
needs_slm |= prog_data->total_shared;
}
- return get_default_l3_weights(&pipeline->device->info,
- needs_dc, needs_slm);
+ return gen_get_default_l3_weights(&pipeline->device->info,
+ needs_dc, needs_slm);
}
#define emit_lri(batch, reg, imm) \
@@ -344,9 +69,9 @@ get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
*/
static void
setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
- const struct anv_l3_config *cfg)
+ const struct gen_l3_config *cfg)
{
- const bool has_slm = cfg->n[L3P_SLM];
+ const bool has_slm = cfg->n[GEN_L3P_SLM];
/* According to the hardware docs, the L3 partitioning can only be changed
* while the pipeline is completely drained and the caches are flushed,
@@ -391,27 +116,30 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
#if GEN_GEN >= 8
- assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]);
+ assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
uint32_t l3cr;
anv_pack_struct(&l3cr, GENX(L3CNTLREG),
.SLMEnable = has_slm,
- .URBAllocation = cfg->n[L3P_URB],
- .ROAllocation = cfg->n[L3P_RO],
- .DCAllocation = cfg->n[L3P_DC],
- .AllAllocation = cfg->n[L3P_ALL]);
+ .URBAllocation = cfg->n[GEN_L3P_URB],
+ .ROAllocation = cfg->n[GEN_L3P_RO],
+ .DCAllocation = cfg->n[GEN_L3P_DC],
+ .AllAllocation = cfg->n[GEN_L3P_ALL]);
/* Set up the L3 partitioning. */
emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG), l3cr);
#else
- const bool has_dc = cfg->n[L3P_DC] || cfg->n[L3P_ALL];
- const bool has_is = cfg->n[L3P_IS] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
- const bool has_c = cfg->n[L3P_C] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
- const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
+ const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
+ const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
+ cfg->n[GEN_L3P_ALL];
+ const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
+ cfg->n[GEN_L3P_ALL];
+ const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
+ cfg->n[GEN_L3P_ALL];
- assert(!cfg->n[L3P_ALL]);
+ assert(!cfg->n[GEN_L3P_ALL]);
/* When enabled SLM only uses a portion of the L3 on half of the banks,
* the matching space on the remaining banks has to be allocated to a
@@ -420,11 +148,11 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
*/
const struct gen_device_info *devinfo = &cmd_buffer->device->info;
const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
- assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
+ assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
/* Minimum number of ways that can be allocated to the URB. */
const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
- assert(cfg->n[L3P_URB] >= n0_urb);
+ assert(cfg->n[GEN_L3P_URB] >= n0_urb);
uint32_t l3sqcr1, l3cr2, l3cr3;
anv_pack_struct(&l3sqcr1, GENX(L3SQCREG1),
@@ -440,19 +168,19 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
.SLMEnable = has_slm,
.URBLowBandwidth = urb_low_bw,
- .URBAllocation = cfg->n[L3P_URB],
+ .URBAllocation = cfg->n[GEN_L3P_URB],
#if !GEN_IS_HASWELL
- .ALLAllocation = cfg->n[L3P_ALL],
+ .ALLAllocation = cfg->n[GEN_L3P_ALL],
#endif
- .ROAllocation = cfg->n[L3P_RO],
- .DCAllocation = cfg->n[L3P_DC]);
+ .ROAllocation = cfg->n[GEN_L3P_RO],
+ .DCAllocation = cfg->n[GEN_L3P_DC]);
anv_pack_struct(&l3cr3, GENX(L3CNTLREG3),
- .ISAllocation = cfg->n[L3P_IS],
+ .ISAllocation = cfg->n[GEN_L3P_IS],
.ISLowBandwidth = 0,
- .CAllocation = cfg->n[L3P_C],
+ .CAllocation = cfg->n[GEN_L3P_C],
.CLowBandwidth = 0,
- .TAllocation = cfg->n[L3P_T],
+ .TAllocation = cfg->n[GEN_L3P_T],
.TLowBandwidth = 0);
/* Set up the L3 partitioning. */
@@ -479,51 +207,15 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
}
-/**
- * Return the unit brw_context::urb::size is expressed in, in KB. \sa
- * gen_device_info::urb::size.
- */
-static unsigned
-get_urb_size_scale(const struct gen_device_info *devinfo)
-{
- return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
-}
-
void
genX(setup_pipeline_l3_config)(struct anv_pipeline *pipeline)
{
- const struct anv_l3_weights w = get_pipeline_state_l3_weights(pipeline);
+ const struct gen_l3_weights w = get_pipeline_state_l3_weights(pipeline);
const struct gen_device_info *devinfo = &pipeline->device->info;
- const struct anv_l3_config *const cfg = get_l3_config(devinfo, w);
- pipeline->urb.l3_config = cfg;
-
- unsigned sz = cfg->n[L3P_URB] * get_l3_way_size(devinfo);
-
-#if GEN_GEN == 9
- /* From the SKL "L3 Allocation and Programming" documentation:
- *
- * "URB is limited to 1008KB due to programming restrictions. This is not
- * a restriction of the L3 implementation, but of the FF and other clients.
- * Therefore, in a GT4 implementation it is possible for the programmed
- * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
- * only 1008KB of this will be used."
- */
- sz = MIN2(1008, sz);
-#endif
- pipeline->urb.total_size = sz / get_urb_size_scale(devinfo);
-}
-
-/**
- * Print out the specified L3 configuration.
- */
-static void
-dump_l3_config(const struct anv_l3_config *cfg)
-{
- fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
- cfg->n[L3P_SLM], cfg->n[L3P_URB], cfg->n[L3P_ALL],
- cfg->n[L3P_DC], cfg->n[L3P_RO],
- cfg->n[L3P_IS], cfg->n[L3P_C], cfg->n[L3P_T]);
+ pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
+ pipeline->urb.total_size =
+ gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
}
void
@@ -531,7 +223,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
const struct anv_pipeline *pipeline)
{
struct anv_cmd_state *state = &cmd_buffer->state;
- const struct anv_l3_config *const cfg = pipeline->urb.l3_config;
+ const struct gen_l3_config *const cfg = pipeline->urb.l3_config;
assert(cfg);
if (cfg != state->current_l3_config) {
setup_l3_config(cmd_buffer, cfg);
@@ -539,7 +231,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
fprintf(stderr, "L3 config transition: ");
- dump_l3_config(cfg);
+ gen_dump_l3_config(cfg, stderr);
}
}
}
--
2.5.0.400.gff86faf
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