[Mesa-dev] [PATCH 02/33] intel/blorp: Take an isl_swizzle instead of a SWIZZLE

[Jason Ekstrand]

---
 src/intel/blorp/blorp.h               |  2 +-
 src/intel/blorp/blorp_blit.c          | 29 ++---------------------------
 src/mesa/drivers/dri/i965/brw_blorp.c | 28 +++++++++++++++++++++++++++-
 3 files changed, 30 insertions(+), 29 deletions(-)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index 12f1833..c06e1cb 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -98,7 +98,7 @@ void
 blorp_blit(struct blorp_batch *batch,
            const struct blorp_surf *src_surf,
            unsigned src_level, unsigned src_layer,
-           enum isl_format src_format, int src_swizzle,
+           enum isl_format src_format, struct isl_swizzle src_swizzle,
            const struct blorp_surf *dst_surf,
            unsigned dst_level, unsigned dst_layer,
            enum isl_format dst_format,
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 97d3745..6dee170 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -21,7 +21,6 @@
  * IN THE SOFTWARE.
  */
 
-#include "program/prog_instruction.h"
 #include "compiler/nir/nir_builder.h"
 
 #include "blorp_priv.h"
@@ -1248,25 +1247,6 @@ brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform,
    }
 }
 
-/**
- * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
- * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
- *
- * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
- *         0          1          2          3             4            5
- *         4          5          6          7             0            1
- *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
- *
- * which is simply adding 4 then modding by 8 (or anding with 7).
- *
- * We then may need to apply workarounds for textureGather hardware bugs.
- */
-static enum isl_channel_select
-swizzle_to_scs(GLenum swizzle)
-{
-   return (enum isl_channel_select)((swizzle + 4) & 7);
-}
-
 static void
 surf_convert_to_single_slice(const struct isl_device *isl_dev,
                              struct brw_blorp_surface_info *info)
@@ -1383,7 +1363,7 @@ void
 blorp_blit(struct blorp_batch *batch,
            const struct blorp_surf *src_surf,
            unsigned src_level, unsigned src_layer,
-           enum isl_format src_format, int src_swizzle,
+           enum isl_format src_format, struct isl_swizzle src_swizzle,
            const struct blorp_surf *dst_surf,
            unsigned dst_level, unsigned dst_layer,
            enum isl_format dst_format,
@@ -1640,12 +1620,7 @@ blorp_blit(struct blorp_batch *batch,
 
    brw_blorp_get_blit_kernel(batch->blorp, &params, &wm_prog_key);
 
-   params.src.view.swizzle = (struct isl_swizzle) {
-      .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
-      .g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
-      .b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
-      .a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
-   };
+   params.src.view.swizzle = src_swizzle;
 
    batch->blorp->exec(batch, &params);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index c902f2e..44d2570 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -256,6 +256,25 @@ brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
 }
 
 /**
+ * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
+ * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
+ *
+ * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
+ *         0          1          2          3             4            5
+ *         4          5          6          7             0            1
+ *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
+ *
+ * which is simply adding 4 then modding by 8 (or anding with 7).
+ *
+ * We then may need to apply workarounds for textureGather hardware bugs.
+ */
+static enum isl_channel_select
+swizzle_to_scs(GLenum swizzle)
+{
+   return (enum isl_channel_select)((swizzle + 4) & 7);
+}
+
+/**
  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
  * the physical layer holding sample 0.  So, for example, if
@@ -332,10 +351,17 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
    blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true,
                           &dst_level, &tmp_surfs[2]);
 
+   struct isl_swizzle src_isl_swizzle = {
+      .r = swizzle_to_scs(GET_SWZ(src_swizzle, 0)),
+      .g = swizzle_to_scs(GET_SWZ(src_swizzle, 1)),
+      .b = swizzle_to_scs(GET_SWZ(src_swizzle, 2)),
+      .a = swizzle_to_scs(GET_SWZ(src_swizzle, 3)),
+   };
+
    struct blorp_batch batch;
    blorp_batch_init(&brw->blorp, &batch, brw);
    blorp_blit(&batch, &src_surf, src_level, src_layer,
-              brw_blorp_to_isl_format(brw, src_format, false), src_swizzle,
+              brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
               &dst_surf, dst_level, dst_layer,
               brw_blorp_to_isl_format(brw, dst_format, true),
               src_x0, src_y0, src_x1, src_y1,
-- 
2.5.0.400.gff86faf