[Mesa-dev] [PATCH 2/2] i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).

[Ilia Mirkin]

On Wed, Nov 30, 2016 at 3:00 PM, Plamena Manolova
<plamena.manolova at intel.com> wrote:
> This extension allows the fragment shader to control whether values in
> gl_SampleMaskIn[] reflect the coverage after application of the early
> depth and stencil tests.
>
> Signed-off-by: Plamena Manolova <plamena.manolova at intel.com>
> ---
>  docs/relnotes/13.1.0.html                    |  1 +

Also docs/features.txt :)

[I think the patch looks fine otherwise, but you should wait for an
Intel person to review it for real.]

>  src/mesa/drivers/dri/i965/brw_compiler.h     |  1 +
>  src/mesa/drivers/dri/i965/brw_fs.cpp         |  1 +
>  src/mesa/drivers/dri/i965/gen8_ps_state.c    | 13 ++++++++++---
>  src/mesa/drivers/dri/i965/intel_extensions.c |  1 +
>  5 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes/13.1.0.html
> index 4f76cc2..a160cda 100644
> --- a/docs/relnotes/13.1.0.html
> +++ b/docs/relnotes/13.1.0.html
> @@ -45,6 +45,7 @@ Note: some of the new features are only available with certain drivers.
>
>  <ul>
>  <li>GL_NV_image_formats on any driver supporting GL_ARB_shader_image_load_store (i965, nvc0, radeonsi, softpipe)</li>
> +<li>GL_ARB_post_depth_coverage on i965/gen9+</li>

This is generally a sorted list. Should go first.

>  </ul>
>
>  <h2>Bug fixes</h2>
> diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
> index 65a7478..410641f 100644
> --- a/src/mesa/drivers/dri/i965/brw_compiler.h
> +++ b/src/mesa/drivers/dri/i965/brw_compiler.h
> @@ -397,6 +397,7 @@ struct brw_wm_prog_data {
>     bool computed_stencil;
>
>     bool early_fragment_tests;
> +   bool post_depth_coverage;
>     bool dispatch_8;
>     bool dispatch_16;
>     bool dual_src_blend;
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index c218f56..ce0c07e 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -6454,6 +6454,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
>         shader->info->outputs_read);
>
>     prog_data->early_fragment_tests = shader->info->fs.early_fragment_tests;
> +   prog_data->post_depth_coverage = shader->info->fs.post_depth_coverage;
>
>     prog_data->barycentric_interp_modes =
>        brw_compute_barycentric_interp_modes(compiler->devinfo, shader);
> diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> index a4eb962..33ef023 100644
> --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> @@ -53,10 +53,17 @@ gen8_upload_ps_extra(struct brw_context *brw,
>        dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
>
>     if (prog_data->uses_sample_mask) {
> -      if (brw->gen >= 9)
> -         dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
> -      else
> +      if (brw->gen >= 9) {
> +         if (prog_data->post_depth_coverage) {
> +            dw1 |= BRW_PCICMS_DEPTH << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
> +         }
> +         else {
> +            dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT;
> +         }
> +      }
> +      else {
>           dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
> +      }
>     }
>
>     if (prog_data->uses_omask)
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
> index 66079b5..19f4684 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -415,6 +415,7 @@ intelInitExtensions(struct gl_context *ctx)
>        ctx->Extensions.KHR_texture_compression_astc_ldr = true;
>        ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
>        ctx->Extensions.MESA_shader_framebuffer_fetch = true;
> +      ctx->Extensions.ARB_post_depth_coverage = true;
>     }
>
>     if (ctx->API == API_OPENGL_CORE)
> --
> 2.7.4
>