[Mesa-dev] [PATCH] i965: Emit proper NOPs.

[Ian Romanick]

On 12/05/2016 12:24 PM, Matt Turner wrote:
> The PRMs for HSW and newer say that other than the opcode and DebugCtrl
> bits of the instruction word, the rest must be zero.
> 
> By zeroing the instruction word manually, we avoid using any of the
> state inherited through brw_codegen.
> 
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=96959
     ^zilla

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>

> ---
>  src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index cfb3fa0..ca04221 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -1282,10 +1282,8 @@ brw_F16TO32(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
>  void brw_NOP(struct brw_codegen *p)
>  {
>     brw_inst *insn = next_insn(p, BRW_OPCODE_NOP);
> -   brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_1);
> -   brw_set_dest(p, insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
> -   brw_set_src0(p, insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
> -   brw_set_src1(p, insn, brw_imm_ud(0x0));
> +   memset(insn, 0, sizeof(*insn));
> +   brw_inst_set_opcode(p->devinfo, insn, BRW_OPCODE_NOP);
>  }
>  
>  
>