[Mesa-dev] [PATCH 4/7] i965: Replace opencoding of brw_load_register_imm32

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

On 09/12/16 10:54, Chris Wilson wrote:
> There are a few open coded setting of single registers using
> MI_LOAD_REGISTER_IMM, replace those with a call to
> brw_load_register_imm32().
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>   src/mesa/drivers/dri/i965/brw_draw.c         |  6 +-----
>   src/mesa/drivers/dri/i965/brw_state_upload.c | 13 +++++--------
>   src/mesa/drivers/dri/i965/gen7_l3_state.c    | 20 ++++++++------------
>   src/mesa/drivers/dri/i965/gen8_depth_state.c |  8 +++-----
>   4 files changed, 17 insertions(+), 30 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
> index 52589d0d13..b78e73516e 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> @@ -239,11 +239,7 @@ brw_emit_prim(struct brw_context *brw,
>         } else {
>            brw_load_register_mem32(brw, GEN7_3DPRIM_START_INSTANCE, bo,
>                                    prim->indirect_offset + 12);
> -         BEGIN_BATCH(3);
> -         OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
> -         OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
> -         OUT_BATCH(0);
> -         ADVANCE_BATCH();
> +         brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
>         }
>      } else {
>         indirect_flag = 0;
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index b689ae41f6..ea58bf02cf 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -399,14 +399,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
>      brw_upload_invariant_state(brw);
>   
>      /* Recommended optimization for Victim Cache eviction in pixel backend. */
> -   if (brw->gen >= 9) {
> -      BEGIN_BATCH(3);
> -      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
> -      OUT_BATCH(GEN7_CACHE_MODE_1);
> -      OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
> -                GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
> -      ADVANCE_BATCH();
> -   }
> +   if (brw->gen >= 9)
> +      brw_load_register_imm32(brw,
> +                              GEN7_CACHE_MODE_1,
> +                              REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
> +                              GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
>   
>      if (brw->gen >= 8) {
>         gen8_emit_3dstate_sample_pattern(brw);
> diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> index e746b995c1..dd68f036b3 100644
> --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
> @@ -117,21 +117,17 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
>                                  PIPE_CONTROL_CS_STALL);
>   
>      if (brw->gen >= 8) {
> -      assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
> +      uint32_t partition;
>   
> -      BEGIN_BATCH(3);
> -      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
> +      assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
>   
>         /* Set up the L3 partitioning. */
> -      OUT_BATCH(GEN8_L3CNTLREG);
> -      OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
> -                SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
> -                SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
> -                SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
> -                SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
> -
> -      ADVANCE_BATCH();
> -
> +      partition = has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0;
> +      partition |= SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC);
> +      partition |= SET_FIELD(cfg->n[GEN_L3P_RO],  GEN8_L3CNTLREG_RO_ALLOC);
> +      partition |= SET_FIELD(cfg->n[GEN_L3P_DC],  GEN8_L3CNTLREG_DC_ALLOC);
> +      partition |= SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC);
> +      brw_load_register_imm32(brw, GEN8_L3CNTLREG, partition);
>      } else {
>         assert(!cfg->n[GEN_L3P_ALL]);
>   
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index 14689f400f..71e5831cf1 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -347,11 +347,9 @@ gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
>                                  render_cache_flush);
>   
>      /* CACHE_MODE_1 is a non-privileged register. */
> -   BEGIN_BATCH(3);
> -   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
> -   OUT_BATCH(GEN7_CACHE_MODE_1);
> -   OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
> -   ADVANCE_BATCH();
> +   brw_load_register_imm32(brw,
> +                           GEN7_CACHE_MODE_1,
> +                           GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
>   
>      /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
>       * Flush bits is often necessary.  We do it regardless because it's easier.