[Mesa-dev] [PATCH 7/7] i965: Reorder parameters to brw_store_register_mem
Lionel Landwerlin
lionel.g.landwerlin at intel.com
Fri Dec 9 11:59:22 UTC 2016
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
On 09/12/16 10:54, Chris Wilson wrote:
> Reorder the parameters to brw_store_register_mem32 and
> brw_store_register_mem64 so that the offset into the buffer and its
> identifier are paired. This brings the interface into line wth
> brw_load_register_mem.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
> src/mesa/drivers/dri/i965/brw_performance_monitor.c | 3 ++-
> src/mesa/drivers/dri/i965/brw_pipelined_register.c | 8 ++++++--
> src/mesa/drivers/dri/i965/brw_pipelined_register.h | 4 ++--
> src/mesa/drivers/dri/i965/gen6_queryobj.c | 21 ++++++++++++---------
> src/mesa/drivers/dri/i965/gen7_sol_state.c | 5 ++---
> src/mesa/drivers/dri/i965/hsw_sol.c | 16 +++++++++-------
> 6 files changed, 33 insertions(+), 24 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
> index 1b991bfafa..e198525f8f 100644
> --- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c
> +++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c
> @@ -589,8 +589,9 @@ snapshot_statistics_registers(struct brw_context *brw,
> assert(ctx->PerfMonitor.Groups[group].Counters[i].Type ==
> GL_UNSIGNED_INT64_AMD);
>
> - brw_store_register_mem64(brw, monitor->pipeline_stats_bo,
> + brw_store_register_mem64(brw,
> brw->perfmon.statistics_registers[i],
> + monitor->pipeline_stats_bo,
> offset + i * sizeof(uint64_t));
> }
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.c b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
> index 0b226035e7..6b6b2487e8 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipelined_register.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.c
> @@ -81,7 +81,9 @@ brw_load_register_mem64(struct brw_context *brw,
> */
> void
> brw_store_register_mem32(struct brw_context *brw,
> - drm_intel_bo *bo, uint32_t reg, uint32_t offset)
> + uint32_t reg,
> + drm_intel_bo *bo,
> + uint32_t offset)
> {
> assert(brw->gen >= 6);
>
> @@ -107,7 +109,9 @@ brw_store_register_mem32(struct brw_context *brw,
> */
> void
> brw_store_register_mem64(struct brw_context *brw,
> - drm_intel_bo *bo, uint32_t reg, uint32_t offset)
> + uint32_t reg,
> + drm_intel_bo *bo,
> + uint32_t offset)
> {
> assert(brw->gen >= 6);
>
> diff --git a/src/mesa/drivers/dri/i965/brw_pipelined_register.h b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
> index 7730f4cad7..1904ae4a54 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipelined_register.h
> +++ b/src/mesa/drivers/dri/i965/brw_pipelined_register.h
> @@ -38,12 +38,12 @@ void brw_load_register_mem64(struct brw_context *brw,
> uint32_t offset);
>
> void brw_store_register_mem32(struct brw_context *brw,
> - drm_intel_bo *bo,
> uint32_t reg,
> + drm_intel_bo *bo,
> uint32_t offset);
> void brw_store_register_mem64(struct brw_context *brw,
> - drm_intel_bo *bo,
> uint32_t reg,
> + drm_intel_bo *bo,
> uint32_t offset);
>
> void brw_load_register_imm32(struct brw_context *brw,
> diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
> index ce6813b531..9de83ed50b 100644
> --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
> +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
> @@ -75,12 +75,13 @@ write_primitives_generated(struct brw_context *brw,
> brw_emit_mi_flush(brw);
>
> if (brw->gen >= 7 && stream > 0) {
> - brw_store_register_mem64(brw, query_bo,
> + brw_store_register_mem64(brw,
> GEN7_SO_PRIM_STORAGE_NEEDED(stream),
> - idx * sizeof(uint64_t));
> + query_bo, idx * sizeof(uint64_t));
> } else {
> - brw_store_register_mem64(brw, query_bo, CL_INVOCATION_COUNT,
> - idx * sizeof(uint64_t));
> + brw_store_register_mem64(brw,
> + CL_INVOCATION_COUNT,
> + query_bo, idx * sizeof(uint64_t));
> }
> }
>
> @@ -91,11 +92,13 @@ write_xfb_primitives_written(struct brw_context *brw,
> brw_emit_mi_flush(brw);
>
> if (brw->gen >= 7) {
> - brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream),
> - idx * sizeof(uint64_t));
> + brw_store_register_mem64(brw,
> + GEN7_SO_NUM_PRIMS_WRITTEN(stream),
> + bo, idx * sizeof(uint64_t));
> } else {
> - brw_store_register_mem64(brw, bo, GEN6_SO_NUM_PRIMS_WRITTEN,
> - idx * sizeof(uint64_t));
> + brw_store_register_mem64(brw,
> + GEN6_SO_NUM_PRIMS_WRITTEN,
> + bo, idx * sizeof(uint64_t));
> }
> }
>
> @@ -149,7 +152,7 @@ emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo,
> */
> brw_emit_mi_flush(brw);
>
> - brw_store_register_mem64(brw, bo, reg, idx * sizeof(uint64_t));
> + brw_store_register_mem64(brw, reg, bo, idx * sizeof(uint64_t));
> }
>
>
> diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
> index df1f56a5a6..f91abb46c1 100644
> --- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
> @@ -418,9 +418,8 @@ gen7_save_primitives_written_counters(struct brw_context *brw,
> /* Emit MI_STORE_REGISTER_MEM commands to write the values. */
> for (int i = 0; i < streams; i++) {
> int offset = (obj->prim_count_buffer_index + i) * sizeof(uint64_t);
> - brw_store_register_mem64(brw, obj->prim_count_bo,
> - GEN7_SO_NUM_PRIMS_WRITTEN(i),
> - offset);
> + brw_store_register_mem64(brw, GEN7_SO_NUM_PRIMS_WRITTEN(i),
> + obj->prim_count_bo, offset);
> }
>
> /* Update where to write data to. */
> diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c b/src/mesa/drivers/dri/i965/hsw_sol.c
> index d9c9539199..ac7eae79dd 100644
> --- a/src/mesa/drivers/dri/i965/hsw_sol.c
> +++ b/src/mesa/drivers/dri/i965/hsw_sol.c
> @@ -65,8 +65,9 @@ save_prim_start_values(struct brw_context *brw,
>
> /* Emit MI_STORE_REGISTER_MEM commands to write the values. */
> for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
> - brw_store_register_mem64(brw, obj->prim_count_bo,
> + brw_store_register_mem64(brw,
> GEN7_SO_NUM_PRIMS_WRITTEN(i),
> + obj->prim_count_bo,
> START_OFFSET + i * sizeof(uint64_t));
> }
> }
> @@ -119,7 +120,9 @@ tally_prims_written(struct brw_context *brw,
>
> if (!finalize) {
> /* Write back the new tally */
> - brw_store_register_mem32(brw, obj->prim_count_bo, HSW_CS_GPR(0),
> + brw_store_register_mem32(brw,
> + HSW_CS_GPR(0),
> + obj->prim_count_bo,
> TALLY_OFFSET + i * sizeof(uint32_t));
> } else {
> /* Convert the number of primitives to the number of vertices. */
> @@ -147,8 +150,8 @@ tally_prims_written(struct brw_context *brw,
> ADVANCE_BATCH();
> }
> /* Store it to the final result */
> - brw_store_register_mem32(brw, obj->prim_count_bo, HSW_CS_GPR(0),
> - i * sizeof(uint32_t));
> + brw_store_register_mem32(brw, HSW_CS_GPR(0),
> + obj->prim_count_bo, i * sizeof(uint32_t));
> }
> }
> }
> @@ -203,9 +206,8 @@ hsw_pause_transform_feedback(struct gl_context *ctx,
>
> /* Save the SOL buffer offset register values. */
> for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++)
> - brw_store_register_mem32(brw, brw_obj->offset_bo,
> - GEN7_SO_WRITE_OFFSET(i),
> - i * sizeof(uint32_t));
> + brw_store_register_mem32(brw, GEN7_SO_WRITE_OFFSET(i),
> + brw_obj->offset_bo, i * sizeof(uint32_t));
> }
>
> /* Add any primitives written to our tally */
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