[Mesa-dev] [PATCH] i965/gen8: Enable hiz for all depth levels

[Ben Widawsky]

On Thu, Jan 28, 2016 at 05:31:43PM -0800, Ben Widawsky wrote:
> From: Jordan Justen <jordan.l.justen at intel.com>
> 
> After modifying the hiz buffer allocation and qpitch calculation, hiz
> appears to work in all cases on gen8.
> 
> v2 by Ben: add GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR. From docs:
> "If the depth buffer clear operation does clear the entire width and height of
> the surface, then the “full surface clear” bit in 3DSTATE_WM_OP must be set to
> 1."
> I'm very surprised that no regressions were spotted originally.
> 
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com> (v1)
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com> (v1)
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com> (v2)
> ---
> 
> I am currently running perf data on this patch, but we might not see an
> improvement (Jordan didn't last time around). However, I think using more HiZ is
> general a good thing, and we should merge the patch unless we have perf
> regressions.
> 
> Jenkins shows no regressions except on BXT where I have no data.

I ran the perf data on this (BDW GT3). In my admittedly limited data set, I
don't really see any difference. As you pointed out today, this is optimizing
the less interesting case since the feature is about bandwidth savings, and
we're already doing this for LOD0 (arguably the level with the highest savings).

So, I think we should probably merge this patch given that I have no jenkins
regressions, but, it might be nice to collect perf data on HSW, and SKL as well,
just to make sure. *shrug*

[snip]