[Mesa-dev] [PATCH 2/6] i965/fs: Add an enum for keeping track of texture instruciton sources
Jason Ekstrand
jason at jlekstrand.net
Sat Feb 6 05:20:25 UTC 2016
These logical texture instructions can have a *lot* of sources. It's much
safer if we have symbolic names for them.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 46 +++++++++++++++-------------
src/mesa/drivers/dri/i965/brw_fs.h | 14 +++++++++
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 19 ++++++++----
3 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 41a3f81..8f4a7c1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -739,18 +739,20 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
- assert(src[8].file == IMM && src[9].file == IMM);
+ assert(src[FS_TEX_SRC_COORD_COMPONENTS].file == IMM &&
+ src[FS_TEX_SRC_GRAD_COMPONENTS].file == IMM);
/* Texture coordinates. */
- if (i == 0)
- return src[8].ud;
+ if (i == FS_TEX_SRC_COORDINATE)
+ return src[FS_TEX_SRC_COORD_COMPONENTS].ud;
/* Texture derivatives. */
- else if ((i == 2 || i == 3) && opcode == SHADER_OPCODE_TXD_LOGICAL)
- return src[9].ud;
+ else if ((i == FS_TEX_SRC_LOD || i == FS_TEX_SRC_LOD2) &&
+ opcode == SHADER_OPCODE_TXD_LOGICAL)
+ return src[FS_TEX_SRC_GRAD_COMPONENTS].ud;
/* Texture offset. */
- else if (i == 7)
+ else if (i == FS_TEX_SRC_OFFSET_VALUE)
return 2;
/* MCS */
- else if (i == 5 && opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL)
+ else if (i == FS_TEX_SRC_MCS && opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL)
return 2;
else
return 1;
@@ -4080,17 +4082,18 @@ static void
lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
{
const brw_device_info *devinfo = bld.shader->devinfo;
- const fs_reg &coordinate = inst->src[0];
- const fs_reg &shadow_c = inst->src[1];
- const fs_reg &lod = inst->src[2];
- const fs_reg &lod2 = inst->src[3];
- const fs_reg &sample_index = inst->src[4];
- const fs_reg &mcs = inst->src[5];
- const fs_reg &sampler = inst->src[6];
- const fs_reg &offset_value = inst->src[7];
- assert(inst->src[8].file == IMM && inst->src[9].file == IMM);
- const unsigned coord_components = inst->src[8].ud;
- const unsigned grad_components = inst->src[9].ud;
+ const fs_reg &coordinate = inst->src[FS_TEX_SRC_COORDINATE];
+ const fs_reg &shadow_c = inst->src[FS_TEX_SRC_SHADOW_C];
+ const fs_reg &lod = inst->src[FS_TEX_SRC_LOD];
+ const fs_reg &lod2 = inst->src[FS_TEX_SRC_LOD2];
+ const fs_reg &sample_index = inst->src[FS_TEX_SRC_SAMPLE_INDEX];
+ const fs_reg &mcs = inst->src[FS_TEX_SRC_MCS];
+ const fs_reg &sampler = inst->src[FS_TEX_SRC_SAMPLER];
+ const fs_reg &offset_value = inst->src[FS_TEX_SRC_OFFSET_VALUE];
+ assert(inst->src[FS_TEX_SRC_COORD_COMPONENTS].file == IMM);
+ const unsigned coord_components = inst->src[FS_TEX_SRC_COORD_COMPONENTS].ud;
+ assert(inst->src[FS_TEX_SRC_GRAD_COMPONENTS].file == IMM);
+ const unsigned grad_components = inst->src[FS_TEX_SRC_GRAD_COMPONENTS].ud;
if (devinfo->gen >= 7) {
lower_sampler_logical_send_gen7(bld, inst, op, coordinate,
@@ -4384,7 +4387,7 @@ get_lowered_simd_width(const struct brw_device_info *devinfo,
case SHADER_OPCODE_TG4_OFFSET_LOGICAL: {
/* gather4_po_c is unsupported in SIMD16 mode. */
- const fs_reg &shadow_c = inst->src[1];
+ const fs_reg &shadow_c = inst->src[FS_TEX_SRC_SHADOW_C];
return (shadow_c.file != BAD_FILE ? 8 : inst->exec_size);
}
case SHADER_OPCODE_TXL_LOGICAL:
@@ -4393,7 +4396,7 @@ get_lowered_simd_width(const struct brw_device_info *devinfo,
* Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
* mode because the message exceeds the maximum length of 11.
*/
- const fs_reg &shadow_c = inst->src[1];
+ const fs_reg &shadow_c = inst->src[FS_TEX_SRC_SHADOW_C];
if (devinfo->gen == 4 && shadow_c.file == BAD_FILE)
return 16;
else if (devinfo->gen < 7 && shadow_c.file != BAD_FILE)
@@ -4416,7 +4419,8 @@ get_lowered_simd_width(const struct brw_device_info *devinfo,
* circumstances it can end up with a message that is too long in SIMD16
* mode.
*/
- const unsigned coord_components = inst->src[8].ud;
+ const unsigned coord_components =
+ inst->src[FS_TEX_SRC_COORD_COMPONENTS].ud;
/* First three arguments are the sample index and the two arguments for
* the MCS data.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 4612a28..4a38f80 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -66,6 +66,20 @@ offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
return reg;
}
+enum fs_tex_src_type {
+ FS_TEX_SRC_COORDINATE,
+ FS_TEX_SRC_SHADOW_C,
+ FS_TEX_SRC_LOD,
+ FS_TEX_SRC_LOD2,
+ FS_TEX_SRC_SAMPLE_INDEX,
+ FS_TEX_SRC_MCS,
+ FS_TEX_SRC_SAMPLER,
+ FS_TEX_SRC_OFFSET_VALUE,
+ FS_TEX_SRC_COORD_COMPONENTS,
+ FS_TEX_SRC_GRAD_COMPONENTS,
+ FS_TEX_SRC_MAX,
+};
+
/**
* The fragment shader front-end.
*
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a74ed72..e41a99d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -145,13 +145,20 @@ fs_visitor::emit_texture(ir_texture_opcode op,
* samples, so don't worry about them.
*/
fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1));
- const fs_reg srcs[] = {
- coordinate, shadow_c, lod, lod2,
- sample_index, mcs, sampler_reg, offset_value,
- brw_imm_d(coord_components), brw_imm_d(grad_components)
- };
- enum opcode opcode;
+ fs_reg srcs[FS_TEX_SRC_MAX];
+ srcs[FS_TEX_SRC_COORDINATE] = coordinate;
+ srcs[FS_TEX_SRC_SHADOW_C] = shadow_c;
+ srcs[FS_TEX_SRC_LOD] = lod;
+ srcs[FS_TEX_SRC_LOD2] = lod2;
+ srcs[FS_TEX_SRC_SAMPLE_INDEX] = sample_index;
+ srcs[FS_TEX_SRC_MCS] = mcs;
+ srcs[FS_TEX_SRC_SAMPLER] = sampler_reg;
+ srcs[FS_TEX_SRC_OFFSET_VALUE] = offset_value;
+ srcs[FS_TEX_SRC_COORD_COMPONENTS] = brw_imm_d(coord_components);
+ srcs[FS_TEX_SRC_GRAD_COMPONENTS] = brw_imm_d(grad_components);
+
+ enum opcode opcode;
switch (op) {
case ir_tex:
opcode = SHADER_OPCODE_TEX_LOGICAL;
--
2.5.0.400.gff86faf
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