[Mesa-dev] [PATCH v2 08/20] gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS
Ilia Mirkin
imirkin at alum.mit.edu
Sat Feb 6 23:50:34 UTC 2016
On Sat, Feb 6, 2016 at 5:04 PM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> This cap indicates the supported representations of programs. It should
> be a flag with the pipe_shader_ir enum values. It will allow to enable
> ARB_compute_shader if the underlying driver supports TGSI.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
> src/gallium/auxiliary/gallivm/lp_bld_limits.h | 2 ++
> src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 ++
> src/gallium/docs/source/screen.rst | 2 ++
> src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++
> src/gallium/drivers/ilo/ilo_screen.c | 2 ++
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
> src/gallium/drivers/r300/r300_screen.c | 4 ++++
> src/gallium/drivers/r600/r600_pipe.c | 2 ++
> src/gallium/drivers/radeonsi/si_pipe.c | 5 +++++
> src/gallium/drivers/svga/svga_screen.c | 6 ++++++
> src/gallium/drivers/vc4/vc4_screen.c | 2 ++
> src/gallium/include/pipe/p_defines.h | 1 +
> 12 files changed, 32 insertions(+)
>
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
> index 4598db8..a123b4a 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
> @@ -128,6 +128,8 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
> return PIPE_MAX_SHADER_SAMPLER_VIEWS;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 1 << PIPE_SHADER_IR_TGSI;
> case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
> return 1;
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h
> index 26fec8e..c807af9 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
> +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
> @@ -465,6 +465,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
> return PIPE_MAX_SHADER_SAMPLER_VIEWS;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 1 << PIPE_SHADER_IR_TGSI;
Everywhere else you return 0, but here and above you return TGSI...
> case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
> return 1;
> case PIPE_SHADER_CAP_DOUBLES:
> diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst
> index 3324bcc..ee8b446 100644
> --- a/src/gallium/docs/source/screen.rst
> +++ b/src/gallium/docs/source/screen.rst
> @@ -415,6 +415,8 @@ to be 0.
> (also used to implement atomic counters). Having this be non-0 also
> implies support for the ``LOAD``, ``STORE``, and ``ATOM*`` TGSI
> opcodes.
> +* ``PIPE_SHADER_CAP_SUPPORTED_IRS``: Supported representations of the
> + program. It should be a flag with the ``pipe_shader_ir`` enum values.
... be a mask of ``pipe_shader_ir`` bits
perhaps that'd be more clear?
>
>
> .. _pipe_compute_cap:
> diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
> index 27f4d26..5387ef3 100644
> --- a/src/gallium/drivers/freedreno/freedreno_screen.c
> +++ b/src/gallium/drivers/freedreno/freedreno_screen.c
> @@ -434,6 +434,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
> return 16;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
> return 32;
> case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
> diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c
> index 44d7c11..ef9da6b 100644
> --- a/src/gallium/drivers/ilo/ilo_screen.c
> +++ b/src/gallium/drivers/ilo/ilo_screen.c
> @@ -136,6 +136,8 @@ ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
> return ILO_MAX_SAMPLER_VIEWS;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
> return 1;
> case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index d368fda..2b12de4 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -272,6 +272,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
> switch (param) {
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
> case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
> case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
> diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c
> index a2b7f87..877ec65 100644
> --- a/src/gallium/drivers/r300/r300_screen.c
> +++ b/src/gallium/drivers/r300/r300_screen.c
> @@ -324,6 +324,8 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, e
> return 32;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> }
> break;
> case PIPE_SHADER_VERTEX:
> @@ -383,6 +385,8 @@ static int r300_get_shader_param(struct pipe_screen *pscreen, unsigned shader, e
> return 32;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> }
> break;
> }
> diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
> index 9d37801..95737ad 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -536,6 +536,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
> } else {
> return PIPE_SHADER_IR_TGSI;
> }
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_DOUBLES:
> if (rscreen->b.family == CHIP_CYPRESS ||
> rscreen->b.family == CHIP_CAYMAN || rscreen->b.family == CHIP_ARUBA)
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 61ce976..26ce8d1 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -461,6 +461,9 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
> #else
> return PIPE_SHADER_IR_NATIVE;
> #endif
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> +
> case PIPE_SHADER_CAP_DOUBLES:
> return HAVE_LLVM >= 0x0307;
>
> @@ -524,6 +527,8 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
> return 16;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_DOUBLES:
> return HAVE_LLVM >= 0x0307;
> case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
> diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c
> index d5405f8..f77c5c2 100644
> --- a/src/gallium/drivers/svga/svga_screen.c
> +++ b/src/gallium/drivers/svga/svga_screen.c
> @@ -468,6 +468,8 @@ vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
> return 16;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_DOUBLES:
> case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
> @@ -527,6 +529,8 @@ vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
> return 0;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_DOUBLES:
> case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
> @@ -619,6 +623,8 @@ vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
> return SVGA3D_DX_MAX_SAMPLERS;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_DOUBLES:
> case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
> diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c
> index b19d31a..181a879 100644
> --- a/src/gallium/drivers/vc4/vc4_screen.c
> +++ b/src/gallium/drivers/vc4/vc4_screen.c
> @@ -357,6 +357,8 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
> return VC4_MAX_TEXTURE_SAMPLERS;
> case PIPE_SHADER_CAP_PREFERRED_IR:
> return PIPE_SHADER_IR_TGSI;
> + case PIPE_SHADER_CAP_SUPPORTED_IRS:
> + return 0;
> case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
> return 32;
> case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
> diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
> index 800f16c..6a67fd9 100644
> --- a/src/gallium/include/pipe/p_defines.h
> +++ b/src/gallium/include/pipe/p_defines.h
> @@ -719,6 +719,7 @@ enum pipe_shader_cap
> PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
> PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT,
> PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
> + PIPE_SHADER_CAP_SUPPORTED_IRS,
> };
>
> /**
> --
> 2.6.4
>
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