[Mesa-dev] [PATCH 08/23] i965: Allow fast clear to be used with lossless compression

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 871a77e..5391794 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -227,7 +227,10 @@ get_fast_clear_rect(struct brw_context *brw, struct gl_framebuffer *fb,
    unsigned int x_align, y_align;
    unsigned int x_scaledown, y_scaledown;
 
-   if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE) {
+   switch (irb->mt->msaa_layout) {
+   case INTEL_MSAA_LAYOUT_CSS:
+      assert(brw->gen >= 9);
+   case INTEL_MSAA_LAYOUT_NONE:
       /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
        * Target(s)", beneath the "Fast Color Clear" bullet (p327):
        *
@@ -278,7 +281,8 @@ get_fast_clear_rect(struct brw_context *brw, struct gl_framebuffer *fb,
        */
       x_align *= 2;
       y_align *= 2;
-   } else {
+      break;
+   default:
       /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
        * Target(s)", beneath the "MSAA Compression" bullet (p326):
        *
-- 
2.5.0