[Mesa-dev] [PATCH] winsys/radeon: fix a wrong NUM_TILE_PIPES value from the kernel

[Alexandre Demers]

On Tue, 9 Feb 2016 at 12:47 Marek Olšák <maraeo at gmail.com> wrote:

> On Tue, Feb 9, 2016 at 6:17 PM, Alexandre Demers
> <alexandre.f.demers at gmail.com> wrote:
> >> +            /* The kernel returns 12 for some cards for an unknown
> >> reason.
> >> +             * I thought this was supposed to be a power of two.
> >> +             */
> >> +            if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
> >> +                ws->info.num_tile_pipes = 8;
> >> +
> >
> > I may be late in the conversation, but shouldn't we have a look at why
> the
> > value reported by the kernel is wrong for "some" cards? Which ones and
> why
> > should be identified. It seems to be limited to Southern Islands as far
> as
> > we know for now, which limits the scope for now.
> >
> > Also, about the patch itself, even if only some cards were reported to be
> > problematic, why would we limit it to "ws->gen == DRV_SI"? Any cards
> > reporting a wrong value should be treated the same way by mapping its
> value
> > from 12 to 8, no?
>
> No. Only one card is affected (Tahiti or Pitcairn, I don't remember
> which one). No other card reports 12.
>
> There is no point in looking into why the value is wrong and I haven't
> been able to find where the value had come from. It's part of the
> kernel ABI now anyway. Userspace won't use it anymore.
>
> Marek
>
Well, meanwhile, I went on and I had a look at the kernel settings. Here is
the answer and the "problem":

This was returned by radeon_info_ioctl(), case RADEON_INFO_NUM_TILE_PIPES,
else if (rdev->family >= CHIP_TAHITI) *value =
rdev->config.si.max_tile_pipes;
(
http://lxr.free-electrons.com/source/drivers/gpu/drm/radeon/radeon_kms.c#L353
)

Searching where max_tile_pipes was set, it seems the value comes from
si_gpu_init(), case CHIP_TAHITI, rdev->config.si.max_tile_pipes = 12
(
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/radeon/si.c
)

This is probably wrong, all other GPU having a power of 2 value (I had a
look at ni.c, si.c, evergreen.c). Either that or we have a special case for
Tahiti.

Also, if this is a special case, while comparing how things works between
si.c and cik.c, I saw that (si | cik)_tiling_mode_table_init() were not
exactly mapping gpus the same way: si.c uses the family, while cik.c uses
the max_tile_pipes value and defaults any value over 8 to be treated as 16.

If this can be of any help / reflection...
Alexandre Demers
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