[Mesa-dev] [PATCH 8/8] gallium/radeon: fix c++11-narrowing errors

[Rob Herring]

In builds with clang, there are several errors related to the enum
alu_op_flags like this:

src/gallium/drivers/r600/sb/sb_expr.cpp:887:8: error: case value evaluates to -1610612736, which cannot be narrowed to type 'unsigned int' [-Wc++11-narrowing]

These are due to the MSB being set in the enum. Fix these errors by
making the enum values unsigned as needed. The flags field that stores
this enum also needs to be unsigned.

Cc: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Rob Herring <robh at kernel.org>
---
 src/gallium/drivers/r600/r600_isa.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_isa.h b/src/gallium/drivers/r600/r600_isa.h
index 27fc1e8..b3f49bd 100644
--- a/src/gallium/drivers/r600/r600_isa.h
+++ b/src/gallium/drivers/r600/r600_isa.h
@@ -102,13 +102,13 @@ enum alu_op_flags
 
 	/* condition codes - 3 bits */
 	AF_CC_SHIFT = 29,
-	AF_CC_MASK	= (7 << AF_CC_SHIFT),
-	AF_CC_E		= (0 << AF_CC_SHIFT),
-	AF_CC_GT	= (1 << AF_CC_SHIFT),
-	AF_CC_GE	= (2 << AF_CC_SHIFT),
-	AF_CC_NE	= (3 << AF_CC_SHIFT),
-	AF_CC_LT	= (4 << AF_CC_SHIFT),
-	AF_CC_LE	= (5 << AF_CC_SHIFT),
+	AF_CC_MASK	= (7U << AF_CC_SHIFT),
+	AF_CC_E		= (0U << AF_CC_SHIFT),
+	AF_CC_GT	= (1U << AF_CC_SHIFT),
+	AF_CC_GE	= (2U << AF_CC_SHIFT),
+	AF_CC_NE	= (3U << AF_CC_SHIFT),
+	AF_CC_LT	= (4U << AF_CC_SHIFT),
+	AF_CC_LE	= (5U << AF_CC_SHIFT),
 };
 
 /* flags for FETCH instructions (TEX/VTX) */
@@ -165,7 +165,7 @@ struct alu_op_info
 	 * (0 if instruction doesn't exist for chip class) */
 	int	slots[4];
 	/* flags (mostly autogenerated from instruction name) */
-	int	flags;
+	unsigned int flags;
 };
 
 /* FETCH instruction info */
-- 
2.5.0