[Mesa-dev] [PATCH 1/4] i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.

[Alejandro Piñeiro]

Looks good to me:

Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>

On 01/07/16 07:07, Francisco Jerez wrote:
> Shouldn't cause any functional changes at this point, but we have
> forgotten to apply this workaround several times in the past, make
> sure it doesn't happen again.
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c   |  9 ---------
>  src/mesa/drivers/dri/i965/brw_pipe_control.c | 21 +++++++++++----------
>  src/mesa/drivers/dri/i965/intel_fbo.c        |  8 --------
>  src/mesa/drivers/dri/i965/intel_tex.c        |  8 --------
>  4 files changed, 11 insertions(+), 35 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 690c2f6..c3d341f 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -925,15 +925,6 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
>        const unsigned dc_flush =
>           brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
>  
> -      if (brw->gen == 6) {
> -         /* Hardware workaround: SNB B-Spec says:
> -          *
> -          *   Before a PIPE_CONTROL with Write Cache Flush Enable = 1, a
> -          *   PIPE_CONTROL with any non-zero post-sync-op is required.
> -          */
> -         brw_emit_post_sync_nonzero_flush(brw);
> -      }
> -
>        brw_emit_pipe_control_flush(brw,
>                                    PIPE_CONTROL_RENDER_TARGET_FLUSH |
>                                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 4672efd..586355d 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -109,6 +109,17 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
>        OUT_BATCH(0);
>        ADVANCE_BATCH();
>     } else if (brw->gen >= 6) {
> +      if (brw->gen == 6 &&
> +          (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
> +         /* Hardware workaround: SNB B-Spec says:
> +          *
> +          *   [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
> +          *   Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
> +          *   required.
> +          */
> +         brw_emit_post_sync_nonzero_flush(brw);
> +      }
> +
>        flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
>  
>        BEGIN_BATCH(5);
> @@ -325,16 +336,6 @@ brw_emit_mi_flush(struct brw_context *brw)
>                    PIPE_CONTROL_VF_CACHE_INVALIDATE |
>                    PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
>                    PIPE_CONTROL_CS_STALL;
> -
> -         if (brw->gen == 6) {
> -            /* Hardware workaround: SNB B-Spec says:
> -             *
> -             * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
> -             * Flush Enable =1, a PIPE_CONTROL with any non-zero
> -             * post-sync-op is required.
> -             */
> -            brw_emit_post_sync_nonzero_flush(brw);
> -         }
>        }
>        brw_emit_pipe_control_flush(brw, flags);
>     }
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 939f9a0..707a9d2 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -1061,14 +1061,6 @@ brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo)
>        return;
>  
>     if (brw->gen >= 6) {
> -      if (brw->gen == 6) {
> -         /* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
> -          * Flush Enable = 1, a PIPE_CONTROL with any non-zero
> -          * post-sync-op is required.
> -          */
> -         brw_emit_post_sync_nonzero_flush(brw);
> -      }
> -
>        brw_emit_pipe_control_flush(brw,
>                                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                                    PIPE_CONTROL_RENDER_TARGET_FLUSH |
> diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
> index a802d5a..8c32fe3 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex.c
> @@ -364,14 +364,6 @@ intel_texture_barrier(struct gl_context *ctx)
>     struct brw_context *brw = brw_context(ctx);
>  
>     if (brw->gen >= 6) {
> -      if (brw->gen == 6) {
> -         /* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
> -          * Flush Enable = 1, a PIPE_CONTROL with any non-zero
> -          * post-sync-op is required.
> -          */
> -         brw_emit_post_sync_nonzero_flush(brw);
> -      }
> -
>        brw_emit_pipe_control_flush(brw,
>                                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                                    PIPE_CONTROL_RENDER_TARGET_FLUSH |