[Mesa-dev] [PATCH] gallium/radeon: add and use radeon_info::max_alloc_size (v2)
Vedran Miletić
vedran at miletic.net
Mon Jul 4 10:37:36 UTC 2016
Reviewed-by: Vedran Miletić <vedran at miletic.net>
On 07/01/2016 04:18 PM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> v2: - squashed the patches
> - use INT_MAX
> - clamp max_const_buffer_size
> - check the DRM version in radeon
> ---
> src/gallium/drivers/r600/r600_pipe.c | 4 ++--
> src/gallium/drivers/radeon/r600_pipe_common.c | 11 +++++------
> src/gallium/drivers/radeon/radeon_winsys.h | 1 +
> src/gallium/drivers/radeonsi/si_pipe.c | 4 ++--
> src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 2 ++
> src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 ++++
> 6 files changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
> index 119c76b..f23daf9 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -301,7 +301,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
> return 0;
>
> case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
> - return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
> + return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
>
> case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
> return R600_MAP_BUFFER_ALIGNMENT;
> @@ -509,7 +509,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
> pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
> PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
> &max_const_buffer_size);
> - return max_const_buffer_size;
> + return MIN2(max_const_buffer_size, INT_MAX);
>
> } else {
> return R600_MAX_CONST_BUFFER_SIZE;
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 74674e7..f75fa6c 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -864,8 +864,8 @@ static int r600_get_compute_param(struct pipe_screen *screen,
> * 4 * MAX_MEM_ALLOC_SIZE.
> */
> *max_global_size = MIN2(4 * max_mem_alloc_size,
> - rscreen->info.gart_size +
> - rscreen->info.vram_size);
> + MAX2(rscreen->info.gart_size,
> + rscreen->info.vram_size));
> }
> return sizeof(uint64_t);
>
> @@ -889,10 +889,7 @@ static int r600_get_compute_param(struct pipe_screen *screen,
> if (ret) {
> uint64_t *max_mem_alloc_size = ret;
>
> - /* XXX: The limit in older kernels is 256 MB. We
> - * should add a query here for newer kernels.
> - */
> - *max_mem_alloc_size = 256 * 1024 * 1024;
> + *max_mem_alloc_size = rscreen->info.max_alloc_size;
> }
> return sizeof(uint64_t);
>
> @@ -1098,6 +1095,8 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
> printf("chip_class = %i\n", rscreen->info.chip_class);
> printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
> printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
> + printf("max_alloc_size = %i MB\n",
> + (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
> printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
> printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
> printf("has_sdma = %i\n", rscreen->info.has_sdma);
> diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
> index afb970e..1ba288a 100644
> --- a/src/gallium/drivers/radeon/radeon_winsys.h
> +++ b/src/gallium/drivers/radeon/radeon_winsys.h
> @@ -253,6 +253,7 @@ struct radeon_info {
> uint32_t gart_page_size;
> uint64_t gart_size;
> uint64_t vram_size;
> + uint64_t max_alloc_size;
> bool has_dedicated_vram;
> bool has_virtual_memory;
> bool gfx_ib_pad_with_type2;
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index ad2a86a..57c3fbd 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -419,7 +419,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
> HAVE_LLVM >= 0x0307 ? 410 : 330;
>
> case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
> - return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
> + return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
>
> case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
> return 0;
> @@ -566,7 +566,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
> pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
> PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
> &max_const_buffer_size);
> - return max_const_buffer_size;
> + return MIN2(max_const_buffer_size, INT_MAX);
> }
> default:
> /* If compute shaders don't require a special value
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
> index 72afc76..3f5a6f0 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
> @@ -263,6 +263,8 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
> /* Set hardware information. */
> ws->info.gart_size = gtt.heap_size;
> ws->info.vram_size = vram.heap_size;
> + /* TODO: the kernel reports vram/gart.max_allocation == 251 MB (bug?) */
> + ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size);
> /* convert the shader clock from KHz to MHz */
> ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
> ws->info.max_se = ws->amdinfo.num_shader_engines;
> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> index c4d28ff..1b32c37 100644
> --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> @@ -373,6 +373,10 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
> ws->info.gart_size = gem_info.gart_size;
> ws->info.vram_size = gem_info.vram_size;
>
> + ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size);
> + if (ws->info.drm_minor < 40)
> + ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
> +
> /* Get max clock frequency info and convert it to MHz */
> radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
> &ws->info.max_shader_clock);
>
--
Vedran Miletić
vedran.miletic.net
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