[Mesa-dev] [PATCH 1/2] radeon/vce: increase cpb height alignment
Christian König
deathsimple at vodafone.de
Mon Jul 4 18:27:11 UTC 2016
Am 04.07.2016 um 17:46 schrieb Leo Liu:
> Height should be aligned with 2 macroblocks, thus making safer
> for tiled mode
>
> Signed-off-by: Leo Liu <leo.liu at amd.com>
For both patches Reviewed-by: Christian König <christian.koenig at amd.com>.
> ---
> src/gallium/drivers/radeon/radeon_vce.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
> index e8aac8e..92cb8ce 100644
> --- a/src/gallium/drivers/radeon/radeon_vce.c
> +++ b/src/gallium/drivers/radeon/radeon_vce.c
> @@ -454,7 +454,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
>
> get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
> cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
> - cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
> + cpb_size = cpb_size * align(tmp_surf->npix_y, 32);
> cpb_size = cpb_size * 3 / 2;
> cpb_size = cpb_size * enc->cpb_num;
> if (enc->dual_pipe)
More information about the mesa-dev
mailing list