[Mesa-dev] [ANNOUNCE] mesa 12.0.0
Emil Velikov
emil.l.velikov at gmail.com
Fri Jul 8 14:54:27 UTC 2016
Hi all,
It's a real honour to announce Mesa 12.0.0.
This release has massive amount of features, but without a doubt the biggest
ones are:
- Vulkan driver for Intel hardware from Ivy Bridge onward.
- OpenGL 4.3 for nvc0, radeonsi and i965 (Gen8+)
- OpenGL ES 3.1 on nvc0 and radeonsi
- GLVND support for GLX, OpenGL
- New gallium software driver - SWR.
- DRI3 enablement for VDPAU, OMX and VAAPI
Note:
- Gallium radeon drivers (r300, r600 and radeonsi) now require kernel 3.2 and
LLVM 3.6 or later.
- Building SWR requires python2, since some of the generated files cannot be
distributed as part of the release tarball.
To check the full changelog, consisting of more than 5k8 commits from over 120
developers use the following command
git log 11.2-branchpoint..mesa-12.0.0
Important changes since RC4:
- People using git tarballs and/or otherwise retrieving the sources no longer
require to generate their own git_sha1.h file.
- SWR no longer ships LLVM version specific sources. Thus the explicit python2
requirement above.
Changes since -rc4.
Akihiko Odaki (1):
mesa: don't install GLX files if GLX is not built
Ardinartsev Nikita (1):
i965: Avoid division by zero.
Chuck Atkins (2):
swr: Refactor checks for compiler feature flags
gallium: Force blend color to 16-byte alignment
Dave Airlie (3):
virgl: reduce some limits for now
st/glsl_to_tgsi: don't increase immediate index by 1.
Revert "st/glsl_to_tgsi: don't increase immediate index by 1."
Emil Velikov (10):
Revert "swr: Refactor checks for compiler feature flags"
clover: conditionally use MESA_GIT_SHA1
anv: use cache uuid based on the build timestamp.
automake: don't mandate git_sha1.h/MESA_GIT_SHA1
swr: automake: don't ship LLVM version specific generated sources
anv: install the intel_icd.json to ${datarootdir} by default
anv: vulkan: remove the anv_device.$(OBJEXT) rule
bugzilla_mesa.sh: Drop "Bug " from sed command
Update version to 12.0.0(final)
docs: Update 12.0.0 release notes
Ian Romanick (1):
mapi: Export all GLES 3.1 functions in libGLESv2.so
Ilia Mirkin (5):
translate: fix start_instance parameter in sse version
nv50,nvc0: fix start_instance in manual push path
glsl: only match gl_FragData and not gl_SecondaryFragDataEXT
nvc0: when mapping directly, provide accurate xfer info + start
glsl: don't try to lower non-gl builtins as if they were gl_FragData
Jason Ekstrand (38):
spirv: Use the system value version of gl_FrontFace
anv/cmd: Move flush_descriptor_sets to anv_cmd_buffer.c
anv/cmd: Move emit_descriptor_pointers to genX_cmd_buffer.c
anv/cmd: Dirty descriptor sets when a new pipeline is bound
i965/gen4: Pull texture formats from the texture object not the miptree
i965/gen4-6: Handle gl_texture_object::BaseLevel and MinLayer correctly
i965: Drop the maximum 3D texture size to 512 on Sandy Bridge
i965/blorp/gen8: Use the correct max level and layer in emit_surface_states
i965/gen8: Use the qpitch from the aux_mt for AUX_QPITCH
i965/fs: Use a default Y coordinate of 0 for TXF on gen9+
i965/gen4: Subtract 1 from buffer sizes
genxml/gen8,9: Prefix the multisample format enum with MSFMT
isl/state: Don't use designated initializers for the surface state
isl/state: Remove some unused fields
isl/state: Put surface format setup at the top
isl/state: Put all dimension setup together and towards the top
isl/state: Put pitch calculations together
isl/state: Return an extent3d from the halign/valign helper
isl/state: Refactor the per-gen isl_to_gen_h/valign tables
isl/state: Refactor the setup of clear colors
isl/state: Don't force-disable L2 bypass for everything
isl/state: Set SurfaceArray based on the surface dimension
isl/state: Don't set RenderTargetViewExtent for texture surfaces
isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels
isl/state: Set the IntegerSurfaceFormat bit on Haswell
isl/state: Use the layout for computing qpitch rather than dimensions
isl/state: Only set cube face enables if usage includes CUBE_BIT
isl/state: Emit no-op mip tail setup on SKL
isl/state: Use TILEWALK_XMAJOR for linear surfaces on gen7
isl/state: Don't set SurfacePitch for gen9 1-D textures
isl/state: Add assertions for buffer surface restrictions
isl/state: Don't use designated initializers for buffer surface state
isl/state: Allow for full 31-bit buffer texture sizes
anv,isl: Lower storage image formats in anv
genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7
anv: Add an allocator for scratch buffers
genxml: Make ScratchSpaceBasePointer an address instead of an offset
anv: Use different BOs for different scratch sizes and stages
Jordan Justen (3):
i965: Preserve the internal format of the dri image
i965: Skip update_texture_surface when the plane doesn't exist
i965: Use miptree to decide format on multi-plane images for gen < 7
José Fonseca (1):
include: Require MSVC 2013 Update 4.
Kenneth Graunke (12):
i965: Reorganize prog_data->total_scratch code a bit.
glsl: Make constant propagation's folder not propagate into an LHS.
glsl: Split arrays even in the presence of whole-array copies.
glsl: Propagate invariant/precise after lowering const arrays.
i965: Copy propagate before doing variable index lowering.
glsl: Make lower_const_arrays_to_uniforms work directly on constants.
glsl: Don't constant propagate arrays.
i965: Combine 3DSTATE_STREAMOUT emitters and genX_sol_state atoms.
i965: Implement rasterizer discard via SOL unless required for queries.
i965: Set fs_inst::base_mrf = -1 by default.
glsl: Ignore ir_texture in lower_const_arrays_to_uniforms.
i965: Make emit_urb_writes() not produce an EOT message for GS.
Lionel Landwerlin (1):
anv/wsi: create swapchain images using specified image usage
Marek Olšák (3):
radeonsi: fix a compute shader hang with big threadgroups on SI & CI
radeonsi: fix fractional odd tessellation spacing for Polaris
radeonsi: set PA_SU_SMALL_PRIM_FILTER_CNTL register on Polaris
Mathias Fröhlich (1):
osmesa: Export OSMesaCreateContextAttribs.
Neha Bhende (1):
svga: Fix failures caused in fedora 24
Nicolai Hähnle (4):
radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris
radeonsi: drop the DRAW_PREAMBLE packet on Polaris
st/mesa: an incomplete texture may have a zero-size first image
st/mesa: check the texture image level in st_texture_match_image
Rob Clark (3):
freedreno: fix crash on smaller gpus and higher resolutions
i965: don't drop const initializers in vector splitting
glsl: add driconf to zero-init unintialized vars
Samuel Pitoiset (7):
gm107/ir: make use of IMUL32I for all immediates
gm107/ir: make use of MOV32I for all immediates
gm107/ir: make use of LOP32I for all immediates
gm107/ir: add missing setcond flags for LOP variants
gm107/ir: make sure that flagsDef is set when emitting setcond
gm107/ir: fix sign bit emission for FADD32I
nvc0/ir: reset the base offset for indirect images accesses
Tim Rowley (1):
swr: push/pop DEBUG macro around llvm includes
sonjiang (3):
radeon: uvd add uvd fw version for amdgpu
radeon/uvd: separate uvd context buffer from DPB
radeon/uvd: fix a h265 context size bug
git tag: mesa-12.0.0
ftp://ftp.freedesktop.org/pub/mesa/12.0.0/mesa-12.0.0.tar.gz
MD5: 98e7ee527b7db48f794cde6496562d2b mesa-12.0.0.tar.gz
SHA1: 88c0aedc3aba4c490141b39ca69418f9dd8c5e45 mesa-12.0.0.tar.gz
SHA256: 3b8fa4d86d78f8f6ec86055b92ad1afe869001483593b3dd4531184b8bc4fcfb mesa-12.0.0.tar.gz
PGP: ftp://ftp.freedesktop.org/pub/mesa/12.0.0/mesa-12.0.0.tar.gz.sig
ftp://ftp.freedesktop.org/pub/mesa/12.0.0/mesa-12.0.0.tar.xz
MD5: c805c347b6a85cde622845e3fb225aa5 mesa-12.0.0.tar.xz
SHA1: 58379cc681b78eab20a78fa9c4ef8ec021ed65bb mesa-12.0.0.tar.xz
SHA256: 0090c025219318935124292b482e3439bc43e8c074ad01086449fcad88547dc6 mesa-12.0.0.tar.xz
PGP: ftp://ftp.freedesktop.org/pub/mesa/12.0.0/mesa-12.0.0.tar.xz.sig
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