[Mesa-dev] [PATCH 12/13] rfc! i965: Add intel_batchbuffer_flush_fence()
Chad Versace
chad.versace at intel.com
Sat Jul 9 00:01:02 UTC 2016
A variant of intel_batchbuffer_flush() with parameters for in and out
fence fds.
TODO: The i915 kernel interface is not yet upstream.
TODO: The fence variants of libdrm functions drm_intel_*_exec() are not
upstream.
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 30 +++++++++++++++++++--------
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 14 +++++++------
2 files changed, 29 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 5a0db9f..63a96ef 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -320,7 +320,7 @@ throttle(struct brw_context *brw)
/* TODO: Push this whole function into bufmgr.
*/
static int
-do_flush_locked(struct brw_context *brw)
+do_flush_locked(struct brw_context *brw, int in_fence_fd, int *out_fence_fd)
{
struct intel_batchbuffer *batch = &brw->batch;
int ret = 0;
@@ -353,12 +353,17 @@ do_flush_locked(struct brw_context *brw)
if (unlikely(INTEL_DEBUG & DEBUG_AUB))
brw_annotate_aub(brw);
+ /* TODO(chadv): The fence variants of drm_intel_*_exec() are not
+ * upstream.
+ */
if (brw->hw_ctx == NULL || batch->ring != RENDER_RING) {
- ret = drm_intel_bo_mrb_exec(batch->bo, 4 * USED_BATCH(*batch),
- NULL, 0, 0, flags);
+ ret = drm_intel_bo_mrb_fence_exec(batch->bo, 4 * USED_BATCH(*batch),
+ NULL, 0, 0, flags,
+ in_fence_fd, out_fence_fd);
} else {
- ret = drm_intel_gem_bo_context_exec(batch->bo, brw->hw_ctx,
- 4 * USED_BATCH(*batch), flags);
+ ret = drm_intel_gem_bo_context_fence_exec(batch->bo, brw->hw_ctx,
+ 4 * USED_BATCH(*batch), flags,
+ in_fence_fd, out_fence_fd);
}
}
@@ -379,9 +384,17 @@ do_flush_locked(struct brw_context *brw)
return ret;
}
+/**
+ * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
+ * of the fd.
+ *
+ * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
+ * of the returned fd.
+ */
int
-_intel_batchbuffer_flush(struct brw_context *brw,
- const char *file, int line)
+_intel_batchbuffer_flush_fence(struct brw_context *brw,
+ int in_fence_fd, int *out_fence_fd,
+ const char *file, int line)
{
int ret;
@@ -420,7 +433,7 @@ _intel_batchbuffer_flush(struct brw_context *brw,
/* Check that we didn't just wrap our batchbuffer at a bad time. */
assert(!brw->no_batch_wrap);
- ret = do_flush_locked(brw);
+ ret = do_flush_locked(brw, in_fence_fd, out_fence_fd);
if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
fprintf(stderr, "waiting for idle\n");
@@ -436,7 +449,6 @@ _intel_batchbuffer_flush(struct brw_context *brw,
return ret;
}
-
/* This is the only way buffers get added to the validate list.
*/
uint32_t
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 67e8e8f..9376c8d 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -46,14 +46,16 @@ void intel_batchbuffer_save_state(struct brw_context *brw);
void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
void intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
enum brw_gpu_ring ring);
+int _intel_batchbuffer_flush_fence(struct brw_context *brw,
+ int in_fence_fd, int *out_fence_fd,
+ const char *file, int line);
-int _intel_batchbuffer_flush(struct brw_context *brw,
- const char *file, int line);
-
-#define intel_batchbuffer_flush(intel) \
- _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
-
+#define intel_batchbuffer_flush(brw) \
+ _intel_batchbuffer_flush_fence((brw), -1, NULL, __FILE__, __LINE__)
+#define intel_batchbuffer_flush_fence(brw, in_fence_fd, out_fence_fd) \
+ _intel_batchbuffer_flush_fence((brw), (in_fence_fd), (out_fence_fd), \
+ __FILE__, __LINE__)
/* Unlike bmBufferData, this currently requires the buffer be mapped.
* Consider it a convenience function wrapping multple
--
2.9.0.rc2
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