[Mesa-dev] [PATCH 1/2] i965/tcs/scalar: only update imm_offset for second message in 64bit input loads

[Iago Toral Quiroga]

Our indirect URB read messages take both a direct and an indirect offset
so when we emit the second message for a 64-bit input load we can just
always incremement the immediate offset, even for the indirect case.
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 129984a..55383ff 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2507,13 +2507,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
           */
          if (num_iterations > 1) {
             num_components = instr->num_components - 2;
-            if (indirect_offset.file == BAD_FILE) {
-               imm_offset++;
-            } else {
-               fs_reg new_indirect = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
-               bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u));
-               indirect_offset = new_indirect;
-            }
+            imm_offset++;
          }
       }
       break;
-- 
2.1.4