[Mesa-dev] [PATCH 03/95] i965/vec4/nir: allocate two registers for dvec3/dvec4

[Iago Toral Quiroga]

From: Connor Abbott <connor.w.abbott at intel.com>

---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 6662a1e..1f8fa80 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -141,6 +141,9 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl)
       unsigned array_elems =
          reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
 
+      if (reg->bit_size == 64)
+         array_elems *= 2;
+
       nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(array_elems));
    }
 
@@ -270,7 +273,7 @@ dst_reg
 vec4_visitor::get_nir_dest(const nir_dest &dest)
 {
    if (dest.is_ssa) {
-      dst_reg dst = dst_reg(VGRF, alloc.allocate(1));
+      dst_reg dst = dst_reg(VGRF, alloc.allocate(dest.ssa.bit_size / 32));
       nir_ssa_values[dest.ssa.index] = dst;
       return dst;
    } else {
-- 
2.7.4