[Mesa-dev] [PATCH 38/95] i965/vec4: allow the vec4 IR to indicate the execution size of instructions
Iago Toral Quiroga
itoral at igalia.com
Tue Jul 19 10:40:35 UTC 2016
In the vec4 backend the generator sets the execution size for all
instructions to 8, however, we will have to split certain DF instructions
to have an execution size of 4, so we need to indicate this explicitly in the
IR for the generator to set the right execution size for them.
We will use this in a later patch when we implement a SIMD splitting pass.
---
src/mesa/drivers/dri/i965/brw_ir_vec4.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 +
3 files changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 81b6a13..721772e 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -166,6 +166,8 @@ public:
bool sol_final_write; /**< gen6: send commit message */
unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
+ uint8_t exec_size;
+
bool is_send_from_grf();
unsigned regs_read(unsigned arg) const;
bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index d7e6e2d..c6e040e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1526,6 +1526,9 @@ generate_code(struct brw_codegen *p,
}
brw_set_default_exec_size(p, BRW_EXECUTE_4);
fix_exec_size = true;
+ } else {
+ assert(inst->exec_size == 8 || inst->exec_size == 4);
+ brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
}
switch (inst->opcode) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 652b453..265bb17 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -55,6 +55,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
this->mlen = 0;
this->base_mrf = 0;
this->offset = 0;
+ this->exec_size = 8;
this->annotation = NULL;
}
--
2.7.4
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