[Mesa-dev] [PATCH 03/15] i965: add component packing support for load_output intrinsics

[Alejandro Piñeiro]

I miss a little explanation on the commit message (like on commit 8),
but that is just personal preference (and in general I personally tend
to be too verbose on the commit messages).

Either if you add a little explanation or not:

Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>


On 19/07/16 08:33, Timothy Arceri wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 38 +++++++++++++++++++++++++++-----
>  1 file changed, 33 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 395594f..e75e7f7 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -2481,6 +2481,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
>     case nir_intrinsic_load_per_vertex_output: {
>        fs_reg indirect_offset = get_indirect_offset(instr);
>        unsigned imm_offset = instr->const_index[0];
> +      unsigned first_component = nir_intrinsic_component(instr);
>  
>        fs_inst *inst;
>        if (indirect_offset.file == BAD_FILE) {
> @@ -2561,10 +2562,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
>              }
>              bld.LOAD_PAYLOAD(dst, srcs, num_components, 0);
>           } else {
> -            inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, patch_handle);
> +            if (first_component != 0) {
> +               unsigned read_components =
> +                  instr->num_components + first_component;
> +               fs_reg tmp = bld.vgrf(dst.type, read_components);
> +               inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp,
> +                               patch_handle);
> +               inst->regs_written = read_components;
> +               for (unsigned i = 0; i < instr->num_components; i++) {
> +                  bld.MOV(offset(dst, bld, i),
> +                          offset(tmp, bld, i + first_component));
> +               }
> +            } else {
> +               inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst,
> +                               patch_handle);
> +               inst->regs_written = instr->num_components;
> +            }
>              inst->offset = imm_offset;
>              inst->mlen = 1;
> -            inst->regs_written = instr->num_components;
>           }
>        } else {
>           /* Indirect indexing - use per-slot offsets as well. */
> @@ -2574,11 +2589,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
>           };
>           fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
>           bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
> -
> -         inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst, payload);
> +         if (first_component != 0) {
> +            unsigned read_components =
> +               instr->num_components + first_component;
> +            fs_reg tmp = bld.vgrf(dst.type, read_components);
> +            inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
> +                            payload);
> +            inst->regs_written = read_components;
> +            for (unsigned i = 0; i < instr->num_components; i++) {
> +               bld.MOV(offset(dst, bld, i),
> +                       offset(tmp, bld, i + first_component));
> +            }
> +         } else {
> +            inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
> +                            payload);
> +            inst->regs_written = instr->num_components;
> +         }
>           inst->offset = imm_offset;
>           inst->mlen = 2;
> -         inst->regs_written = instr->num_components;
>        }
>        break;
>     }