[Mesa-dev] [PATCH] nvc0: add support for TGSI FMA ops

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>

On 03/09/2016 07:06 AM, Ilia Mirkin wrote:
> This will allow the nouveau backend to not try and split up ops that are
> fused in GLSL.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
>   src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 +++++
>   src/gallium/drivers/nouveau/nvc0/nvc0_screen.c            | 3 ++-
>   2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index 8683722..b06d86a 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -525,6 +525,7 @@ nv50_ir::DataType Instruction::inferSrcType() const
>      case TGSI_OPCODE_DRCP:
>      case TGSI_OPCODE_DSQRT:
>      case TGSI_OPCODE_DMAD:
> +   case TGSI_OPCODE_DFMA:
>      case TGSI_OPCODE_DFRAC:
>      case TGSI_OPCODE_DRSQ:
>      case TGSI_OPCODE_DTRUNC:
> @@ -624,6 +625,7 @@ static nv50_ir::operation translateOpcode(uint opcode)
>      NV50_IR_OPCODE_CASE(SLT, SET);
>      NV50_IR_OPCODE_CASE(SGE, SET);
>      NV50_IR_OPCODE_CASE(MAD, MAD);
> +   NV50_IR_OPCODE_CASE(FMA, FMA);
>      NV50_IR_OPCODE_CASE(SUB, SUB);
>
>      NV50_IR_OPCODE_CASE(FLR, FLOOR);
> @@ -723,6 +725,7 @@ static nv50_ir::operation translateOpcode(uint opcode)
>      NV50_IR_OPCODE_CASE(DRCP, RCP);
>      NV50_IR_OPCODE_CASE(DSQRT, SQRT);
>      NV50_IR_OPCODE_CASE(DMAD, MAD);
> +   NV50_IR_OPCODE_CASE(DFMA, FMA);
>      NV50_IR_OPCODE_CASE(D2I, CVT);
>      NV50_IR_OPCODE_CASE(D2U, CVT);
>      NV50_IR_OPCODE_CASE(I2D, CVT);
> @@ -2672,6 +2675,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>      case TGSI_OPCODE_MAD:
>      case TGSI_OPCODE_UMAD:
>      case TGSI_OPCODE_SAD:
> +   case TGSI_OPCODE_FMA:
>         FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
>            src0 = fetchSrc(0, c);
>            src1 = fetchSrc(1, c);
> @@ -3395,6 +3399,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>         }
>         break;
>      case TGSI_OPCODE_DMAD:
> +   case TGSI_OPCODE_DFMA:
>         FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
>            src0 = getSSA(8);
>            src1 = getSSA(8);
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index 37620ea..eb2bff5 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -333,8 +333,9 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
>         return 1;
>      case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
>         return 1;
> -   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
>      case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
> +      return 1;
> +   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
>      case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
>         return 0;
>      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
>

-- 
-Samuel