[Mesa-dev] [PATCH 05/30] i965/ir: Move base IR definitions into a separate header file.
Francisco Jerez
currojerez at riseup.net
Mon Mar 14 03:47:09 UTC 2016
This pulls out the i965 IR definitions into a separate file and leaves
the top-level backend_shader structure and back-end compiler entry
points in brw_shader.h. The purpose is to keep things tidy and
prevent a nasty circular dependency between brw_cfg.h and
brw_shader.h. The logical dependency between these data structures
looks like:
backend_shader (brw_shader.h) -> cfg_t (brw_cfg.h)
-> bblock_t (brw_cfg.h) -> backend_instruction (brw_shader.h)
This circular header dependency is currently resolved by using forward
declarations of cfg_t/bblock_t in brw_shader.h and having brw_cfg.h
include brw_shader.h, which seems backwards and won't work at all when
the forward declarations of cfg_t/bblock_t are no longer sufficient in
a future commit.
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_ir.h | 164 +++++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_shader.h | 138 +-----------------------
3 files changed, 167 insertions(+), 136 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_ir.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 4689588..1c6d2e9 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -37,6 +37,7 @@ i965_compiler_FILES = \
brw_fs_visitor.cpp \
brw_inst.h \
brw_interpolation_map.c \
+ brw_ir.h \
brw_ir_allocator.h \
brw_ir_fs.h \
brw_ir_vec4.h \
diff --git a/src/mesa/drivers/dri/i965/brw_ir.h b/src/mesa/drivers/dri/i965/brw_ir.h
new file mode 100644
index 0000000..1e4d8c7
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_ir.h
@@ -0,0 +1,164 @@
+/* -*- c++ -*- */
+/*
+ * Copyright © 2010-2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_IR_H
+#define BRW_IR_H
+
+#include "brw_reg.h"
+#include "compiler/glsl/list.h"
+
+#define MAX_SAMPLER_MESSAGE_SIZE 11
+#define MAX_VGRF_SIZE 16
+
+#ifdef __cplusplus
+struct backend_reg : private brw_reg
+{
+ backend_reg() {}
+ backend_reg(const struct brw_reg ®) : brw_reg(reg) {}
+
+ const brw_reg &as_brw_reg() const
+ {
+ assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
+ assert(reg_offset == 0);
+ return static_cast<const brw_reg &>(*this);
+ }
+
+ brw_reg &as_brw_reg()
+ {
+ assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
+ assert(reg_offset == 0);
+ return static_cast<brw_reg &>(*this);
+ }
+
+ bool equals(const backend_reg &r) const;
+
+ bool is_zero() const;
+ bool is_one() const;
+ bool is_negative_one() const;
+ bool is_null() const;
+ bool is_accumulator() const;
+ bool in_range(const backend_reg &r, unsigned n) const;
+
+ /**
+ * Offset within the virtual register.
+ *
+ * In the scalar backend, this is in units of a float per pixel for pre-
+ * register allocation registers (i.e., one register in SIMD8 mode and two
+ * registers in SIMD16 mode).
+ *
+ * For uniforms, this is in units of 1 float.
+ */
+ uint16_t reg_offset;
+
+ using brw_reg::type;
+ using brw_reg::file;
+ using brw_reg::negate;
+ using brw_reg::abs;
+ using brw_reg::address_mode;
+ using brw_reg::subnr;
+ using brw_reg::nr;
+
+ using brw_reg::swizzle;
+ using brw_reg::writemask;
+ using brw_reg::indirect_offset;
+ using brw_reg::vstride;
+ using brw_reg::width;
+ using brw_reg::hstride;
+
+ using brw_reg::f;
+ using brw_reg::d;
+ using brw_reg::ud;
+};
+
+struct bblock_t;
+#endif
+
+#ifdef __cplusplus
+struct backend_instruction : public exec_node {
+ bool is_3src() const;
+ bool is_tex() const;
+ bool is_math() const;
+ bool is_control_flow() const;
+ bool is_commutative() const;
+ bool can_do_source_mods() const;
+ bool can_do_saturate() const;
+ bool can_do_cmod() const;
+ bool reads_accumulator_implicitly() const;
+ bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
+
+ void remove(bblock_t *block);
+ void insert_after(bblock_t *block, backend_instruction *inst);
+ void insert_before(bblock_t *block, backend_instruction *inst);
+ void insert_before(bblock_t *block, exec_list *list);
+
+ /**
+ * True if the instruction has side effects other than writing to
+ * its destination registers. You are expected not to reorder or
+ * optimize these out unless you know what you are doing.
+ */
+ bool has_side_effects() const;
+
+ /**
+ * True if the instruction might be affected by side effects of other
+ * instructions.
+ */
+ bool is_volatile() const;
+#else
+struct backend_instruction {
+ struct exec_node link;
+#endif
+ /** @{
+ * Annotation for the generated IR. One of the two can be set.
+ */
+ const void *ir;
+ const char *annotation;
+ /** @} */
+
+ uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
+ uint8_t mlen; /**< SEND message length */
+ int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
+ uint8_t target; /**< MRT target. */
+ uint8_t regs_written; /**< Number of registers written by the instruction. */
+
+ enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
+ enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
+ enum brw_predicate predicate;
+ bool predicate_inverse:1;
+ bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
+ bool force_writemask_all:1;
+ bool no_dd_clear:1;
+ bool no_dd_check:1;
+ bool saturate:1;
+ bool shadow_compare:1;
+
+ /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
+ * mod and predication.
+ */
+ unsigned flag_subreg:1;
+
+ /** The number of hardware registers used for a message header. */
+ uint8_t header_size;
+};
+
+#endif
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 15bed78..3f38dc1 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -27,146 +27,12 @@
#include "brw_reg.h"
#include "brw_defines.h"
#include "brw_context.h"
-
-#ifdef __cplusplus
-#include "brw_ir_allocator.h"
-#endif
-
-#define MAX_SAMPLER_MESSAGE_SIZE 11
-#define MAX_VGRF_SIZE 16
-
-#ifdef __cplusplus
-struct backend_reg : private brw_reg
-{
- backend_reg() {}
- backend_reg(const struct brw_reg ®) : brw_reg(reg) {}
-
- const brw_reg &as_brw_reg() const
- {
- assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
- assert(reg_offset == 0);
- return static_cast<const brw_reg &>(*this);
- }
-
- brw_reg &as_brw_reg()
- {
- assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
- assert(reg_offset == 0);
- return static_cast<brw_reg &>(*this);
- }
-
- bool equals(const backend_reg &r) const;
-
- bool is_zero() const;
- bool is_one() const;
- bool is_negative_one() const;
- bool is_null() const;
- bool is_accumulator() const;
- bool in_range(const backend_reg &r, unsigned n) const;
-
- /**
- * Offset within the virtual register.
- *
- * In the scalar backend, this is in units of a float per pixel for pre-
- * register allocation registers (i.e., one register in SIMD8 mode and two
- * registers in SIMD16 mode).
- *
- * For uniforms, this is in units of 1 float.
- */
- uint16_t reg_offset;
-
- using brw_reg::type;
- using brw_reg::file;
- using brw_reg::negate;
- using brw_reg::abs;
- using brw_reg::address_mode;
- using brw_reg::subnr;
- using brw_reg::nr;
-
- using brw_reg::swizzle;
- using brw_reg::writemask;
- using brw_reg::indirect_offset;
- using brw_reg::vstride;
- using brw_reg::width;
- using brw_reg::hstride;
-
- using brw_reg::f;
- using brw_reg::d;
- using brw_reg::ud;
-};
-#endif
+#include "brw_ir.h"
struct cfg_t;
-struct bblock_t;
-
-#ifdef __cplusplus
-struct backend_instruction : public exec_node {
- bool is_3src() const;
- bool is_tex() const;
- bool is_math() const;
- bool is_control_flow() const;
- bool is_commutative() const;
- bool can_do_source_mods() const;
- bool can_do_saturate() const;
- bool can_do_cmod() const;
- bool reads_accumulator_implicitly() const;
- bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
-
- void remove(bblock_t *block);
- void insert_after(bblock_t *block, backend_instruction *inst);
- void insert_before(bblock_t *block, backend_instruction *inst);
- void insert_before(bblock_t *block, exec_list *list);
-
- /**
- * True if the instruction has side effects other than writing to
- * its destination registers. You are expected not to reorder or
- * optimize these out unless you know what you are doing.
- */
- bool has_side_effects() const;
-
- /**
- * True if the instruction might be affected by side effects of other
- * instructions.
- */
- bool is_volatile() const;
-#else
-struct backend_instruction {
- struct exec_node link;
-#endif
- /** @{
- * Annotation for the generated IR. One of the two can be set.
- */
- const void *ir;
- const char *annotation;
- /** @} */
-
- uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
- uint8_t mlen; /**< SEND message length */
- int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
- uint8_t target; /**< MRT target. */
- uint8_t regs_written; /**< Number of registers written by the instruction. */
-
- enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
- enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
- enum brw_predicate predicate;
- bool predicate_inverse:1;
- bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
- bool force_writemask_all:1;
- bool no_dd_clear:1;
- bool no_dd_check:1;
- bool saturate:1;
- bool shadow_compare:1;
-
- /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
- * mod and predication.
- */
- unsigned flag_subreg:1;
-
- /** The number of hardware registers used for a message header. */
- uint8_t header_size;
-};
#ifdef __cplusplus
+#include "brw_ir_allocator.h"
enum instruction_scheduler_mode {
SCHEDULE_PRE,
--
2.7.0
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