[Mesa-dev] [PATCH 16/20] radeonsi: implement volatile memory access

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

Prevent loads from being re-ordered or coalesced.

Atomics don't need special handling by definition, and stores don't need
special handling because LLVM is unable to detect dead image or buffer
stores.
---
 src/gallium/drivers/radeonsi/si_shader.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 22296fe..03dc496 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2917,6 +2917,7 @@ static void load_emit(
 		struct lp_build_tgsi_context *bld_base,
 		struct lp_build_emit_data *emit_data)
 {
+	struct si_shader_context *ctx = si_shader_context(bld_base);
 	struct gallivm_state *gallivm = bld_base->base.gallivm;
 	LLVMBuilderRef builder = gallivm->builder;
 	const struct tgsi_full_instruction * inst = emit_data->inst;
@@ -2924,6 +2925,9 @@ static void load_emit(
 	char intrinsic_name[32];
 	char coords_type[8];
 
+	if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
+		emit_optimization_barrier(ctx);
+
 	if (target == TGSI_TEXTURE_BUFFER) {
 		emit_data->output[emit_data->chan] = lp_build_intrinsic(
 			builder, "llvm.amdgcn.buffer.load.format", emit_data->dst_type,
-- 
2.5.0